Hi everyone, pardon me but I'm pretty new to this.
I'm using a Spartan 3 right now, and I'm trying to provide source synchronous clock clocking to a SDR SDRAM using DDR register. The component looks something like this:
OFDDRCPE sdram0OutputClock ( .Q(sdram0_clk), .C0(sdram_clk), .C1(~sdram_clk), .CE(1'b1), .CLR(1'b0), .D0(1'b1), .D1(1'b0), .PRE(1'b0) );
The input clock is sdram_clk and the output clock to the sdram is sdram0_clk The problem is I'm not sure whether I need to specify any extra constraints in the UCF file for sdram0_clk. Is there anything else to take note of? Are sdram_clk and sdram0_clk considered as different clock domains? If so how do I get the data back to the sdram_clk domain?
Thanks in advance, Ben.