Xilinx:CAM

Hi, all, I am implementing an on-chip 16*32 CAM using Xilinx Select RAM(applicatin notes 204 or 260). I am wondering why a register is added to each of the input and output. When I simulate the design in Modelsim, there is always two clock cycles' delay, one for the input register and one for the output register, I guess. So if I specify the data to match, the match output signal will appear after two clock cycles. I don't think it is a correct implementation. Any one has idea about this? Thanks for your answers! regards, Alex

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Alex
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