multiplexing clocks

Hi,

I have three clocks connected to input/output pins (not global clock buffers), and then inside the fpga i have a 3 input multiplexer to select between the three clock signals. I then route the output of the three input multiplexer to a bufg component. I was wondering if this is a valid way to globally route the clock, or if someone has a better idea. ANy help would be appreciated greatly

THank you,

Jonathan

Reply to
Jonathan
Loading thread data ...

Jonathan, the issue could be the asynchronous (?) selection of the clocks. I would assume that you can easily generate glitches, and no circuitry likes uncontrolled glitches on the global clock lines. Virtex global buffers include a mux that can be used to select between two inputs with glich-free operation guaranteed.

Peter Alfke

Reply to
Peter Alfke

I

buffers),

the

multiplexer to

route the

greatly

Reply to
Symon

Yes, I have seen this. THe problem is im trying to select between three clocks. I am using a virtex II. I have 8 GLKP, and I am already using 7 of those global clock pins, leaving me only one left for the output of my three input mux. Is there such an item they have that has a three input bufgmux, or what would be a better solution to this?

Reply to
Jonathan

clocks. I am using a virtex II. I have 8 GLKP, and I am already using 7 of those global clock pins, leaving me only one left for the output of my three input mux. Is there such an item they have that has a three input bufgmux, or what would be a better solution to this?

Reply to
Symon

As I mentioned before, the issue is the asynchronous relationship between the two Select lines and the three clocks. If you want to switch asynchronously, this gets complicated, although not impossible. It would help to know more details like: frequencies, are all three always running (i.e. do you ever switch to or from a stuck clock?)?. Peter Alfke

Reply to
Peter Alfke

Hi

  1. Asynchronus solution The best solution for clock switch is use clock manager logic. Try made clock manager operate with high clock generate by DCM or DLL.The second step is place this component to Virtex (for example constrains.ucf Virtex chips) .The fast step use parameters for phase relation beetwen output clock. I used this method in 24 clock operate system. It works very stable.
  2. Synchronus Switch clock in mux. Try use place too. But if you have more clock better use asynchromus clock manager and set phase relation and placeing. Best regards Wojciech Zebrowski

Uzytkownik napisal w wiadomosci news: snipped-for-privacy@webx.sUNCHnE...

buffers), and then inside the fpga i have a 3 input multiplexer to select between the three clock signals. I then route the output of the three input multiplexer to a bufg component. I was wondering if this is a valid way to globally route the clock, or if someone has a better idea. ANy help would be appreciated greatly

Reply to
FPGA_com

Peter,

All three are always running. They are all around 60 MHz. I never switch to a stuck clock, all three clocks come from an external source that is always running. THe idea is to test each of these clocks. Is the best solution to cascade the bufgmuxes then?

Reply to
Jonathan

I suggest you use two cascaded versions of the circuit I published in XCell, and that you can also find in TechXcusives (#6 of Six Easy Pieces). I know and trust that that circuit works even with asynchronous select inputs, and it is very easy to analyze, since everything is out in the open. You need four slices, since each flip-flop has its own clock. I suppose you could do the same thing with two BUFGMUX circuits, but they are not that easy to analyze. The moment you said "free-running", the problem became trivial. But switching away from a dead clock is a real bear... Peter Alfke

Reply to
Peter Alfke

Can these (BUFGMUX) be used to implement clock-gating? (i.e. if one input is the clock and the other is tied to 0)?

Cheers, Jon

Reply to
Jon Beniston

Jon,

Yes, it is then called a BUFGCE (BUFG with enable).

Aust>

Reply to
Austin Lesea

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.