The Logic Accessible Clocks are entailed for example in
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This was something unique to DDR SDRAM implementation in a now obsolete FPGA family to allow for a local clock in the fabric. Improvements in modern FPGA families make this technique obsolete.
In this implementation the clock input does goes to the data input of a register, but the clock of this register is from a DCM 2X output and there is delay differences between the two that allows for this clock to be captured and then used as data with the logic.
Ed McGettigan
-- Xilinx Inc.
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