Xilinx 3s8000?

Good point, but then I'd be tied into a particular FPGA. The multipliers are very impressive however. If I ever get my design to fit on something, then I can start taking advantage of things like the built-in multipliers to speed things up. Lets see, 18x18->36 bits in less than 5 ns. For a 1024 bit multiply, it would take roughly 1,624 eighteen bit multiplies and a bunch of multi-precision additions, which translates into around 8 microseconds per 1024 bit word! Very impressive indeed.

Ron

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Ron
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P.S. Before someone catches my error, yes indeed you could run some of these multiplies in parallel to cut the timing even more. The datasheet says the Spartan-3E devices have between 4 to 36 dedicated multiplier blocks per device, so depending on how many there are on the FPGA the 8 microseconds I mentioned earlier could be cut by as much as 1/4 to

1/36th to 22ns for 1024 bits!!! I will definitely have to look into this at some point. It would be great if a multiprecision package for the multipliers were already available in Verilog.
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Ron

Reply to
Peter Alfke

Keyboard bounce. ;-)

Reply to
Ron

Since this discussion is veering back and forth between being on-topic, I suppose I can throw my two cents in.

I am both a professional and hobby FPGA developer. At work, I get all kinds of fancy Virtex and Stratix parts to target. At home, I have a Cyclone II 2C35 (on an Altera DE2 board) and the Xilinx sample pack I got for free. Both use free tools from Altera and Xilinx respectively.

First, the silicon is interesting, but not terribly hard anymore. The basic features are common to all manufacturers. The real magic is in the mapping and PAR. Why else would someone pay for Synplicity software? Thus, the software tools that Ron disparages are probably worth the money considering what they do. I recognize that, and accept that it costs money to keep the tools up to date.

That said, I wish vendors didn't feel the need to disown older parts when it isn't difficult to keep support as an option. I can still output from Microsoft Word to all kinds of strange, esoteric (and ancient) formats. Why can't Xilinx allow me to use the latest ISE to target strange, esoteric FPGA's? Simply make it an optional component. At the very least, let me download a support module from your website - if putting it on the DVD is too much trouble.

As it stands, at work I have to keep a copy of ISE 4.2i, because it is the last version that supports the XC4000E series FPGA's - and it doesn't play well when install alongside 7.1i - which means a dedicated terminal just for 4.2i. This is BLOODY FRUSTRATING. I realize the parts are old, but they are still out there - and designs do occasionally need maintenance. BTW - Austin was bragging about a lot of military and space applications. Guys, we actually support those designs for more than 5 years. It would be helpful if your tools did as well.

As for the cost issue, the webpacks cover all but the high-end parts. I have found them perfectly adequate for home use. I'm actually impressed that Xilinx or Altera offer free versions at all. Seriously, you get a VHDL/Verilog compiler, limited simulation, mapping and PAR - for free? That's almost absurd. The only tool I don't have at home is Synplify Pro - I end up using Quartus and XST.

As a fairy tale wish, it would be nice if there was an academic pricing plan that could include guys like me that want to develop at home, without having to run to the office to compile something. Yes, it is a different market - but with just a little forethought, you could offer great pricing to students and hobbyists, while retaining the high-end corporate accounts. I would gladly pay several hundred for a _perpetual_ license that had restrictions on what commercial activities were allowed, yet let me play with the larger parts on boards from Digilent, BurchEd, etc. (I would even be OK with the software being tied TO the boards - maybe lock on the FPGA serial number via JTAG or something)

Much like the GPL, if you want to do something outside the license, like start a business, you cough up for an unrestricted license. Yes, there would be a trust element, but since you are also the manufacturer, it wouldn't be difficult to see a spike in part orders.

Something to think about - since I know I would like to play with the Virtex parts with embedded PPC cores - but can't afford to ante-up to the full package.

Reply to
radarman

blocks.....

The multipliers are built in dedicated logic, so using them will allow you to fit a larger block into a given device. IOW, using them will contribute directly to making your design fit.

--
    Later,
    Jerry.
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Reply to
Jerry Coffin

That's partly because of lawsuits, when Microsoft has attempted to EOL products lines, which has meant excluding still-working-fine PCs.

The short design life of tools has to be impacting their silicon sales, and as you point out, engineering support requires working tools.

-jg

Reply to
Jim Granville

I was wondering about that. There would be a great deal of routing, shifting, etc., in a design that does multi-precision multiplication however, and as slow as the design I'm using now is, it's about as minimal as it's possible to get I think (basically a couple of shift registers, with test and conditional add).

I think I'll go search around and see if I can find some sort of multi-precision multiplication module(s) in Verilog on the net somewhere just to get started quickly. If anyone happens to know of anything like that, please post a link.

Thanks,

Ron

Reply to
Ron

Also look at the newest Lattice devices, they have DSP blocks, with more in them. If you can wear your 'humble and polite researcher' hat, you might be able to get a loan of the full tool chain :) It would be in their interests to have the flow tested on wide data paths.

-jg

Reply to
Jim Granville

Radarman, I agre with most of what you wrote, but I am not the boss here... One exception, though: " Why can't Xilinx allow me to use the latest ISE to target strange, esoteric FPGA's? Simply make it an optional component." Making the newest software compatible with XC3000 nd XC4000 would be a nightmare for our developers. They might declare it so difficult as to be virtually impossible. Backwards compatibility is a nightmare for any software developer (my son works at Apple R&D...) Otherwise you have some good ideas. It's just that our software developer have their plate full with urgent and vital projects, so that the things you mention often don't rise high enough. BTW, at work, I get some anusing comments about the insults I have to endure here. But they are so outlandish that they do not really hurt... Peter Alfke Peter Alfke

Reply to
Peter Alfke

Jim, don't call it research. That word and "play" triggered this whole barrage of Ron's favorite obscenities. Peter

Reply to
Peter Alfke

There are many degrees of compatible :

Easiest, is to first make sure they can co-exist - that's school-boy stuff. ie No real excuse for getting that wrong... [and I think this oops was radarman's main beef..?]

Next degree of compatible is to freeze the back end/command line tools, but keep export of XNF or whatever, so the older P&R tools can be fed from newer front ends.

To make the very newest SW compile to XC4000 is the wrong thing to do.

Not only is it the waste of resource you mention, but it is also poor version-control. Someone doing maint changes, wants to use the _SAME_ tool chain it was created on.

-jg

Reply to
Jim Granville

The unoptimised build of gmp on this bog-standard Athlon X2 4400+ system takes ten microseconds for a 1024x1024->2048 multiply; and there are two processor cores working independently.

I really think you haven't looked enough into what can be done in software before jumping to hardware; gmp-ecm is in the public domain, and Bruce Dodson runs it full-time on a 120-node Opteron cluster at LeHigh university.

Tom

Reply to
Thomas Womack

Tom-

Haha, be careful of what you suggest. Now Ron will need a complimentary Opteron cluster from AMD :-)

-Jeff

Reply to
Jeff Brower

Tom-

Haha, be careful of what you suggest. Now Ron will need a complimentary Opteron cluster from AMD :-)

-Jeff

Reply to
Jeff Brower

Agreed - my primary gripe is that the older versions don't play well with a newer version installed and vice-versa.

Right now, my copy of 7.1 is unusable - and I'll have to get an admin to clean it up to the point where it is usable again. I can manually make it mostly usable by altering the system environment variables - but that's a bit of a pain. To top it off, the 4.2 install doesn't quite work properly either - probably for the same reason. It seems to go through mapping and PAR OK, but I have to create the downloadables on another system. We fought for a week with every part of the toolchain until we switched to another workstation to create the bitstream files - no errors, just corrupt binaries.

When I'm more or less done maintaining the old design, I'm probably going to just wipe both off, and install the latest version again.

Reply to
radarman

Radarman-

I don't understand the struggle. You are violating basic usage principles of ISE. Never a) uninstall and re-install, or b) install a new version on the same machine as an earlier working version. The only thing permitted on any given machine is service pack upgrades within a version. Yes that leaves you with the "5.1 machine", the "6.1 machine", etc. but that's the rule. Your FAE should have told you that; it's all we've ever heard since 1999 and several different FAEs.

-Jeff

Reply to
Jeff Brower

haha, I wouldn't mind one as well. Perhaps it will make my games run smoother :).

Hi Ron,

Are you attempting a 100% hardware solution or are you doing a mix of both hardware and PC software? (Forgive me if this question has already been answered).

-Isaac

Reply to
Isaac Bosompem

Would a VM like VMWare or VPC do the trick, keep your OS with ISE version installed in different virtual boxes. As long as only one runs all the machine resources are available to that VM guest, whether its Linux or Windows.

John Jakson

Reply to
JJ

Hi Isaac.

Yes, as I mentioned to Tom elsewhere in this thread, I have written a

100% Verilog implementation of ECM (as well as Fermat's method and Pollard-Rho). It's runs completely standalone and is not connected to anything except power. It would display the answer (if found) on the development board's LCD display.

I have no objection to using an FPGA as an accelerator for a program running on a conventional computer, but was hoping to fit the entire thing (ECM) on one or more FPGA development boards because that keeps things fast and simple. For me, it's at least as easy to code in Verilog as it is in a typical assembly language, so I see no reason to clutter things up by going off-board or adding a micro-CPU core.

My reasoning is that eventually (hopefully within my lifetime, ha!) FPGA's will become huge and cheap, and I'm hoping that the LUT count of FPGAs increase faster than the performance of traditional computers. That hope may not be justified of course, because some of the same type of technology is used in both CPUs and FPGAs; however, there is no chance that I'll ever be able to afford a cluster of Opterons, but if I can find a way around the exorbitant prices FPGA vendors charge for proprietary software design tools (that can only be used with their own products no less), I could probably afford a fairly high performance FPGA.

In any case, writing ECM in Verilog has been fun and I've learned a lot about Verilog. I now have a working Verilog ECM design, and I'll spend the time until development s/w gets cheap enough for me to afford by tweaking and improving the design. I've been forced to slow my design down to a crawl in order to try to get it to fit into something I can afford, but whenever FPGA's and the requisite design s/w become plentiful and cheap, I hope to be able to take full advantage of all the opportunities for parallelization and pipelining that ECM offers.

Regards,

Ron

Reply to
Ron

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