Xilinx 3s8000?

Thanks for the education. I am always eager to learn. Peter Alfke

Reply to
Peter Alfke
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Ron -

I've seen a lot more valuable input on this newsgroup from Peter and Austin then from you. If you don't want to read comments from the Xilinx folks, then don't. Let the rest of us decide what we want to read and whose opinions we value. As much as I dislike some of the thing Xilinx does, or as much as I gripe about their software, their contributions to this newsgroup are a lot more useful than your rants. Name calling adds nothing to any discussion in this forum.

John Providenza

Reply to
johnp

The Xilinx employees have gone out of their way not to play nice in other discussions reciently, one really has to expect that they set the tone in how they want to be addressed and treated, by how they treat others. Addmittedly Ron is a bit over the top and direct, but so are Austin, Peter, and a few other Xilinx folks that bash others in this forum regularly.

Austin's FUD regarding Grey Market parts hurts Xilinx customers that end up with excess inventory, and the companies that resell or build product using it. Certainly there is conterfeiting fraud of Xilinx parts, just as there is in every industry, including jeans. But the reality is that the main stream Xilinx distributors will not give small businesses the time of day, much less hobbiests. The couple that do, will not stock a full line, and ask for minimum qty purchases on the rest with long lead times that exceed their requirements. Reputable Gray Market sources are a critical resource for hobbiests and small companies, and the FUD just isn't necessary or warranted. Xilinx's "choice" to not support this secondary market is about as helpful as a car dealership unwilling to accept factory warranty service on cars they did not directly sell or lease.

Peter continually goes off half cocked where hobbiests are involved, expecting that they should do their projects like any respectable Fortune 100 company. He's exceptionally proud of their High Margins, which translate to high end customer costs. When Xilinx refuses to open up enough to allow third parties to provide competitive design software tools, including open source alternatives, then being bashed for the high costs of their software is fair game. Especially when they don't play nice with other folks in this forum. And openly disrespect any project that doesn't have a billion dollar ROI.

The size limit of the free web software, also greatly limits what end user boards can be built in volume for this market. Since the high cost of Xilinx tools cuts the market size for boards with larger parts dramatically, so does it drive up the cost of boards ith larger parts because of reduced volume. As I've noted before, this also kills the reconfigurable computing market, with a Xilinx "tax" to use that board each year by paying the high annual subscription costs just to write new software requiring the place, route and bit stream tools. When Xilinx either releases the bit stream generation specifications for their parts, or includes full product line support for place, route and bitstream generation in the free tools, the reasons for bashing them for their software costs will mostly go away.

Till then Xilinx can continue it's FUD regarding second and third teir companies that feed off the Gray Market, crow about the High Margins as a measure of success .... and eat crow from hobbiests and smaller businesses about the high costs and lack of support.

issues independently of cutting off support to compaies that need the Gray Market. It would be a lot better if the tools cost issues where removed and open up the market for boards with larger parts, and third party software. If would be much better, if Xilinx employees didn't bash others here either.

John

Reply to
fpga_toys

Feeling better now Ron ?

First you started asking for help :

"...to work out a deal with the FPGA vendor or someone to lend me the necessary development board and s/w tools in exchange for the potential fame and glory, since I am but a humble retired engineer/hobbyist."

then you later add this:

"..also a $30,000 reward for factoring RSA-704.."

as you are clearly 100% honest, can we take it that the share in the fame and glory you offer, also extends to a share in the (now mentioned) prize ?

or will you donate that to a local school ?

Tip: If you want to succeed in any task, it is better to stay focused, avoiding wasting energies, and also not to alienate any (potential) sources of assistance. Lots of clever people lurk in this news group.

-jg

Reply to
Jim Granville

And a lot of potential, or possibly soon to be EX, customers.

Reply to
fpga_toys

On the contrary, it will hopefully keep them OUT of any discussion threads I may initiate in the future.

Ron

Reply to
Ron

I would feel even better if people like you who have nothing to contribute would stop harassing me.

You must have a reading comprehension problem Jim. I posted a link to the RSA challenge number in my original message that started this thread. Had you bothered to look it up, the $30,000 (up to $200,000 for RSA-2048) was clearly posted on the page I linked to.

With Austin bragging about the 1.73 billion dollars of US sales last year for Xilinx, I figured the $30,000 RSA prize would be inconsequential chicken feed to them, but yes, of course I would be willing to share half of the RSA prize money with *anyone* who would be willing to provide me with at least the design software to complete my project (preferably NOT Xilinx in view of their attitude towards my project).

For that matter, I'd be willing to send someone who already possesses the necessary hardware and software, a copy of the bitstream file so that they could run it themselves on their own hardware. Eventually I'll probably open a SourceForge.com project for it and open source my work, but I'd rather wait until my project comes to fruition first.

Haven't you realized yet that Xilinx reps are a complete waste of my time and energy? They have already made it abundantly clear that they are *NOT* a potential source of assistance to me. At least they could have done so politely without being condescending and rude as though I were some snotty nose kid who hasn't a clue. I wonder what they think I was doing during my 35 year career as an engineer?

I am generally very respectful to those who also show me some respect. For that reason, I can't believe Xilinx let those jerks out of their cages without a leash. "Back in the day" a salesman would never even let an applications engineer visit a customer unaccompanied for fear they would alienate the customer. Now I can see why.

Ron

Reply to
Ron

Why do you write such outrageous lies, just because you like the ring of them? I have never ever mentioned our margins. That's not my style... I also have often bent over backwards to help students and hobbyist, since I remember once havin been one of them myself. (I do discourage people from wasting their time on obsolete chips, though...) I would even have tried to help Ron, if he had presented a rational plan for his endeavor, but he didn't. And then he sank into obscenities...

This used to be a polite, informative and cooperative newsgroup, until you and Ron descended on us, and turned it into an ugly shouting contest. Peter Alfke

Reply to
Peter Alfke

I do not have the time to chase down links, and links are not comprehension...

If you had mentioned that initially, this could have been a more productive thread ?

Well, I was not actually refering to Xilinx (comprehension?)

- you do seem to be rather Xilinx fixated ? :)

-jg

Reply to
Jim Granville

Margins, Profits, Profit Margins? Ring a bell? Hardly lies ... you can run, but you can not hide from your own words. Start with:

"Our primary obligation is to remain an innovative and profitable company, to the benefit of our customers, our employees, and our shareholders. Satisfying exotic academic research is fine, as long as it does not conflict with the primary obligation. Just my personal opinion... Peter Alfke"

remember that discussion, where you support keeping access to Xilinx tools proprietary?

Your arguement in that case was a mock sham about support costs ... total Bovine ....

When Ron is upset about software license costs and annual support fees he mirrors real concerns that cripple your market expansion. You believe that technology is, as you have said, the "crown jewels" ... more like the lead anchor around your companies neck standing on the plank.

There was a day, not that long ago, when pride of craftsmanship would be brought out when you proudly took an older product in for some service help. I do it all the time with my Corvairs, Remington & Underwood Typewritters, Antique Clocks, Hover Vacumn, Packard Bell B&W Tube TV and Radio, etc ... and when the service personel insist on throwing that piece of crap away and buying some new product life engineered for warranty term plus a day, I KNOW I'm dealing with someone that lacks experience, integrity and pride in their products.

Xilinx prides it's self from what I hear, in keeping every old version of software safe. Yet you repeatedly insist that a hobbiest that wants to play with some XC3K should just buy some new fpga instead ... even after he states he's interested in those. A few years back I had $12K in NOS two year old XC4085XL parts, that Xilinx turned their back on and would no longer provide synthesis support for telling me instead to buy new Virtex Parts to use ISE 5.1 with.

Remember? Do you remember your less than helpful tirade regarding a hobbiest/developer needing 5V support? Do you need direct quotes and other references?

yes, you might help people ... and at the same time, are lacking.

And you don't rapidly escalate disagreements and call people an imbecile ... just weeks ago? Remember those words?? ... shall I quote? ... and that's just a start, many more cases .... you can run, but you can not hide from your own words.

Sorry Peter ... how many times have I asked you, Austin, and other Xilinx employees to play nice here and be respectiful, suggesting that you will be treated as you treat others here. That was ignored, and you gleefuly enter into personal attacks and character assassination at the drop of a hat to divert the discussion from the very debatable practices and policies of your employer.

I don't think Ron's choice of words here are the best either ... but neither are yours, or your actions, or those of other Xilinx employees in this forum. Your ranting, stomping, insults, and tirades to deflect valid and justified discussion on flawed Xilinx policy just disgrace this forum worse.

Grossly shameful .... I don't know how anyone could work for a company with employees that lack civility, integrity, and a common sense of respect. And you dare to repeatedly mock me for using a common screen name for my list participation as lacking the integrity to use my own name? What a crock ... but I'm learning that it's the shame of working for a company that also hides behind the alias of Xilinx ... rather than proudly bearing the name of it's founders.

I'm discovering from your actions, that Xilinx is not a company to do business with, or sully the name of my own business representing your products.

So, shall we keep quoting your lies today?

Reply to
fpga_toys

Actually Jim, there is a good reason for that. It almost physically pains me to say something good about Xilinx in view of this thread's history ;-), but their's is the only version of Synplicity that will compile and synthesize my design for anything above a bus width of 256 bits. :-(

Here is the email I received from Synplicity tech support:

Anyone know how to easily track Synplicity bug reports?

Reply to
Ron

It depends on precise details of the implementation, and you have to write moderately ugly code because the x86 multiply instruction produces its outputs in fixed registers, but if you apply Karatsuba-style techniques enough you can get down to below sixty ... one 12x12 requires six 4x4 + some fiddling, one 4x4 requires three

2x2 + some fiddling, one 2x2 requires four, that's 72, or three + extra fiddling to make 54.

However, Karatsuba techniques really work much better on FPGAs where you can do the extra adds in parallel; I don't think you'll gain anything from the three-level decomposition on Opteron.

As you might imagine, I would be ecstatic to see a few wide multipliers appearing in FPGAs - a 64x64->128 unit isn't _that_ large an IP block - but the market for number theorists isn't large enough to pay for the masks, and RSA accelerators are produced in enough volume for it to be worth making ASICs.

Tom

Reply to
Thomas Womack

uh, guy - why the hell u wanna brute force rsa with an fpga. there r quite better (faster and cheaper) methods to do so. hope u calculated the throughput and the years/centurys of trying.

Reply to
frank

Jim Granville schrieb:

Q: Well, what's your opinion on this case, Dr. Freud?

A: A clear case of P.., aehhh Xilinx envy!

SCNR! ;-)

Regards Falk

Reply to
Falk Brunner

Hi Tom. No, a 64x64->128 integer multiplier isn't that large at all. Here is the device utilization report for mine:

Device utilization summary:

--------------------------- Selected Device : 3s500epq208-4 Number of Slices: 557 out of 4656 11% Number of Slice Flip Flops: 370 out of 9312 3% Number of 4 input LUTs: 867 out of 9312 9% Number of bonded IOBs: 18 out of 158 11% Number of GCLKs: 1 out of 24 4%

Keep in mind though that my primary concern at present is minimizing LUT (gate) count, not speed, so this multiplier requires N clock cycles to multiply two N bit numbers together yielding a 2N length result. If you'd like I'll be happy to send you a copy of the Verilog source code for my multiplier and the combination multiplier/modulo module (which is only slightly larger than the multiplier module). It's 110 lines of Verilog.

Regards,

Ron

Reply to
Ron

Example please? RSA-640 was solved with a distributed network of something like 80 Opterons doing sieving. I wouldn't call those "cheap."

That's one of the the shortcomings of ECM that Tom touched on earlier. Unlike traditional factorization methods, ECM doesn't even guarantee any result at all! Because of that, I had to have two status LEDs; one to indicate completion, and another to indicate whether or not a solution was found.

The average throughput rate will hopefully be blazingly fast at about one or two bits per day. ;-) There is no input to the FPGA because the number to be factored is hard coded into the FPGA (although I could easily read it from an external device if needed), and the factor (if found) will be displayed on the board's LCD display, so the only thing connected to the board during operation is power.

Because of the probabilistic nature of ECM, to the best of my knowledge no one has ever been able to calculate how long ECM would require on average for a particular factorization. I wonder if Tom Womack has investigated this in his work with ECM?

Ron

Reply to
Ron

Ron, it's amazing how nice and patient you can be when you want to... Greetings Peter Alfke

Reply to
Peter Alfke

You could use the IMUL instruction (signed multiply) you free yourself from that restriction, you have to make certain that your product will fit in 32-bits and that your values stay in their restricted place (no overflow).

Reply to
Isaac Bosompem

Just for fun, here are the figures for a bus-width of 704 bits and 1024 bits.

Device utilization summary: (704 bit bus-width)

--------------------------- Selected Device : 3s500epq208-4 Number of Slices: 2592 out of 4656 55% Number of Slice Flip Flops: 1779 out of 9312 19% Number of 4 input LUTs: 4176 out of 9312 44% Number of bonded IOBs: 18 out of 158 11% Number of GCLKs: 1 out of 24 4%

Device utilization summary: (1024 bit bus-width)

--------------------------- Selected Device : 3s500epq208-4 Number of Slices: 2975 out of 4656 63% Number of Slice Flip Flops: 2099 out of 9312 22% Number of 4 input LUTs: 4896 out of 9312 52% Number of bonded IOBs: 18 out of 158 11% Number of GCLKs: 1 out of 24 4%

The amazing thing is that the slice and LUT counts seem to increase

*less* than the bus-width increases (ie; the size of the numbers it can multiply). I've taken pains to ensure the optimizer isn't optimizing something away that it shouldn't, so as far as I know these numbers are correct.

The synthesizer reports a maximum frequency of 58MHz for the 64 bit design, 16MHz for the 704 bit design, 12 MHz for the 1024 bit design "as is" without any tweaking to improve the timing, so it should take about

1.1 microseconds to multiply two 64 bit numbers together, and 85 microseconds to multiply two 1024 bit numbers together.

Ron

Reply to
Ron

Presumably you could do it rather quicker using the S3's multiplier blocks.....

Reply to
Mike Harrison

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