Scenario: Multiple identical boards with a Virtex-II each all being fed the same clock signal which is being fed to a DCM on each device.
Lets assume the clock signal has no skew between the FPGAs and all FPGAs get powered/configured at the same time (so the clock signals enter the DCMs in phase).
Will the DCMs achieve lock at the same time and therefore produce output clocks that are in phase relative to each other on all 4 FPGAs? Or will the lock time vary? The datasheet says anything up to for example 120us (for 24-30MHz input, using DLL op) but does this mean a potential phase difference of 120us between the outputs of the DCMs?
What about when multiplying/dividing or using the CLKFX outputs? Does that make a difference?
Many thanks for your time,