Phase alignment of DCMs on different boards/devices

Hi group,

Scenario: Multiple identical boards with a Virtex-II each all being fed the same clock signal which is being fed to a DCM on each device.

Lets assume the clock signal has no skew between the FPGAs and all FPGAs get powered/configured at the same time (so the clock signals enter the DCMs in phase).

Will the DCMs achieve lock at the same time and therefore produce output clocks that are in phase relative to each other on all 4 FPGAs? Or will the lock time vary? The datasheet says anything up to for example 120us (for 24-30MHz input, using DLL op) but does this mean a potential phase difference of 120us between the outputs of the DCMs?

What about when multiplying/dividing or using the CLKFX outputs? Does that make a difference?

Many thanks for your time,

Dave

Reply to
Dave
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Don't count on them being equally fast to lock. There is no "in phase" in distributed systems, strictly speaking. The phase is the delay between clock cycles, so the max phase error is plus minus half the clock.

You can synch multiple devices to within a clock cycle, provided the system is less distributed than a clockcycle is fast, with a trigger pulse. To achieve better synchronization, you need some hardware delay or PLL. Most highend FPGAs do have internal cClock PLLs.

Rene

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Ing.Buero R.Tschaggelar - http://www.ibrtses.com
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Reply to
Rene Tschaggelar

You must distinguish between the relatively long time that th DLL takes to achieve lock (many microseconds) and the very small phase error on the outputs (picoseconds, which is million times shorter) once the DLL is locked

So, the different DLL will most likely achieve lock at different times, but once in lock, they will each perform to data sheet specs, which means picoseconds of difference on the outputs

Another matter is that frequency division can obviously generate out-of-step outputs between different chips.

Peter Alfke, Xilinx

Reply to
Peter Alfke

Hi Peter,

I would have thought that if all DCMs start attempting lock at exactly the same time then they would achieve it at the same time. What causes them to achieve lock at differnt times assuming the input to each is exactly in phase and they start working at the same time? Is it down to differences between the silicon or some other inherent property of the DCMs loop structures?

Many thanks,

Dave

Reply to
Dave

Even if the silicon was identical to the Angstroem, you couldn't guarantee they have the same temperature nor that they see the same supply voltage with the same impedance.

Rene

--
Ing.Buero R.Tschaggelar - http://www.ibrtses.com
& commercial newsgroups - http://www.talkto.net
Reply to
Rene Tschaggelar

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