second flop in asyn reset distribution

You don't have to worry about the leading edge of reset making the second FF go metastable. That case is cleanly asynchronous. The rest of the FSM might go metastable, but that will only last one clock. The next cycle will fix things up. (More likely is a bogus state because of setup timings not reaching all FFs at the same time - simple timing violation.)

You do have to worry about what happens during that clock. Most of the time, the next step downstream will recover. It might be more complicated than that in safety critical applications.

On the trailing edge of reset, you don't have to worry about metastability since the second FF is going from 0 to 0. The first FF might go metastable. You do have to make sure there is enough time on the clock between the first and second FFs to cover that case. You can't get it perfect, just good enough for your application.

(snip)

The probability of metastability effects decreases exponentially with time. Assuming that you have logic between FFs elsewhere in the design there should be plenty of time when there is no logic. That is, when the probability is less than once in the life of the universe, maybe a lot less, that is usually enough.

-- glen

Hi,

there is an interesting paper about this topic. It includes various reset strategies and should clarify your doubts.

It can be found at the following url:

HTH

Ansgar

-- Attention please, reply address is invalid, please remove "_xxx_" ro reply "fpgabuilder" schrieb im Newsbeitrag news: snipped-for-privacy@l41g2000cwc.googlegroups.com...

Thanks everyone.

Well, I guess the question I have is why is that reset is related ot clock only when d input is changing? Can the inverters in the second flop not go metastable when the reset changes but d input does not? AFAIK, this would depend on how the ff is constructed. But the most basic FF that I have studied in past have set and preset input in the feedback loop of the master latch part of the FF.

BTW, Ansgar, thanks for the link. Actually the paper that I reference in my post is the by the same authors Wills and Cummings, as pointed out in your post and when I looked previously there it was the same and did help answer my question.

Metastability requires a race condition. You have to be interested in whether the FF will go from a 0 to a 1 or stay at a 0. (or the other way around)

There is such a race condition when reset goes away if you are trying to clock a 1 into a FF. If you are trying to clock in a 0, there is no problem - you get 0 or 0 so it doesn't matter.

The second FF in the case being discussed is the 0 to 0 case.

The first FF might go metastable. The whole point of this discussion is to move the metastability considerations from all over the FSM to one concentrated place where the designer can check it carefully by hand. The tools don't help much, at least not yet.

Here is a simple explanation: In any conventional flip-flop the asynchronous CLEAR input clears both the master and the slave directly and permanently as long as CLEAR is active. The synchronous RESET is just another (overriding ) input to the logic driving the D input.

All behavior can be deduced from these simple facts

Peter Alfke, Xilinx Applications

Thanks folks.

Hal, I understand at the purpose behind synchronizing the reset. I am curious to find out what goes on inside the flip-flop that does not cause it go metastable when the d input does not change but the reset changes.

Thanks.

So let's take this slowly: You apply asynchronous reset, which forces both latches to 0. There is no metastability as long as CLEAR is active. Then you take away CLEAR asynchronously with repect to the clock. Let's assume the D input is a 1 (if it were a 0, we would not have this dicussion) Both latches are 0 while CLEAR is active,, but if CLEAR goes away right before the clock rising edge, the 1 on D might sneak in and set the master in a metastable way. After the rising clock edge, the master now drives the slave. That means you see a metastable (unbounded) 1 on the slave output Q.

This happens only when the CLEAR goes inactive right before the rising clock edge, and only while D is 1.

(I had this problem once in a FIFO synchronizer, and I solved it by using CLEAR to drive the D input in such a way that the Low on D appears before CLEAR goes Low= inactive. A simple inverter or buffer does the trick, depending on the chosen polarities.) Peter Alfke, Xilinx Applications

Peter, Hal and all.

I was really interested in analysing this at the transistor level which I have now thanks to your inputs and other vlsi references that I looked up.

Thanks.

-sanjay

I'm far from a wizard on the insides of FFs.

To get metastability, you need something like a runt pulse. You get that when 2 inputs to a gate are changing at about the same time.

The simple example is an OR gate. Suppose one input turns off and another turns on a bit later. That will leave a short hole where neither input is turning the output on. If the "bit later" is long enough, you get a clean negative pulse. If it's short enough (maybe negative) you get a clean output with no changes. In between you get runt pulses. (This is easy to setup in the lab.)

If the D input isn't changing, you can still get a runt pulse when the clock and the reset signal change at about the same time. That happens if reset is holding the FF in one state and the D input will change it to the other state on the next clock after reset goes away.

If the D input will produce the same state as reset you don't have any problems.

Most data sheets have setup/hold times for both asynchronous and synchronous resets. In the context of this discussion, an asynchronous reset is safe if you can verify that it meets the setup and hold times. That's possible if it comes from a FF clocked by the same clock. I don't know if the tools support this.

Everything is fine If the asynchronous CLEAR is being used as a synchronous input that conveniently overrides everything on the D input, and it meets the set-up and (usually 0) hold-time requirements. It's when you really have a non-synchronous CLEAR signal coming from a different clock domain or having obscure delay, then you can run into these possibly metastable situations.

Metastability requires a runt pulse to initiate it, but then also a feedback circuit ( i.e. latch) that can hold the runt signal active for an indeterminate time. Luckily, in modern CMOS that time is seldom more than a few nanoseconds, but the length is non-deterministic, described only in statistical terms. XAPP094 and my postings on the TechXcusives on the Xilinx website provide more details. Peter Alfke, Xilinx Applications

For a thorough discussion on metastables, you may find this entry in the FAQ useful:

As to the details of what's going on in a flip-flop, I did a quick search in the Patent data base. Here is a TinyURL to the result:

The first hit: 6,819,156 shows a D flop, no async reset

5,410,194 shows some higher level views of how a simple D flop with some extra logic implements other flops such as T and JK, as well as sync and async load.

You may want to explore. Use keywords like "flip flop", asynchronous, CMOS

Philip Freidin

=================== Philip Freidin snipped-for-privacy@fpga-faq.com Host for

Here is why I think, second ff will not enter the metastable state -

Assume a simple FF with Master-Slave latches constructed of CMOS Pass transistor logic. The CP input is used to gate the pass transistors. The D input is fed to the first pass transistor, T1. O/p of T1 is gated with RESET input and subsequently fed to the second pass transistor, T2.

Normally(or abnormally) a CMOS gate goes metastable if Voh = Vih = Vm/2. The probablity that T2 sees a condition Voh = Vm/2 will only occur if its input changes with CP. Since, D input does not change and IS LOW, the o/p of the RESET & D also does not change, even when RESET changes. Hence, the latch o/p will not go metastable. Therefore, the slave latch will only hold a stable value at the o/p of the FF.

So, Hal, I think your point about runt pulses makes sense. If the ckt happens to enter metastability, then the gain of cmos gates, feed each other and finally knock the o/p into a stable state which is what I think you are saying Peter.

Thanks once again all.