Today I found that a simulation wasn't working right because the set and reset on the flip-flop (dflop) in LTSpice has the set and reset inputs active high. Yet every modern flip-flop is active low. So I had to invert everything on those inputs just for the simulation. The "Special Functions" instructions in LTSPice are silent about this issue.
Does this date back to the days of Methusaleh or what could be the reason?
Connecting unused AND gate inputs to terminal 8 as per instructions also did not work but that was easy to figure out.
The basic digital primitives, (AND, OR, XOR, DFLOP, ...) are independent of any device which you can buy.
Even the handling of not used inputs is different. Simply connect nothing on the unused inputs. The LTspice circuit-compiler will then "remove" these pins to make the circuit as simple as possible for the simulation.
Don't forget to set a rise time or a delay in DFLOP.
Value: td=5n
If you want a Q=1 at the start, then somply add a IC=1.
So they are always active high for control inputs?
In the instructions under "Special Functions" it says, quote "Unused inputs and outputs are to be connected to terminal 8". I guess that's not correct then. At least it fails in my simulation.
Also, one must set Vhigh=3.3V or to whichever logic voltage it is to be. Unfortunately that can't be fed in from any real rail which makes unorthodox stuff such as controlled back-feeding difficult.
In this case I needed to used the CLR pin in a more controlled fashion, where reset happens a few msec after an event.
Same is true in any simulation. The individual devices are evaluated in an arbitrary order. Clock input causes an output change in one FF and the ne xt FF is evaluated after the first, the change will ripple through when it would not in a real part with a finite delay. Kind of a Duh! That's why V HDL has delta delays which still won't protect you if you have any buffers, or other things in the clock path to some FFs (which add a delta delay).
Why is Joerge ranting about LTSpice? Why isn't he at least thanking Helmut for the advice? Helmut is one of the truly knowledgeable people around on LTSpice. He has been a tremendous aid to the community. He also never in sults anyone that I've ever seen.
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That has nothing to do with RF can be perfectly simulated. It's just that the delay numbers are small. In a previous life, when 10kH an 100K were the newest thing, I have built a nice 100K library for the Simucad Silos simulator. That included setup/hold violations etc. I had only a
200 MHz scope, so I had to make sure that at least the logic was OK to start with.
You've got that the wrong way. Low active inputs are a very retro 74xx thing. TTL designers speculated that it took more signal energy to produce a LOW input than a HIGH (correct for TTL) and that would give better noise immunity since most of the time these inputs do nothing.
That has survived for some time only for some things like 74HCT that allowed burning less power without requiring heavy re-thinking.
And no, modern digital design has nothing to do with deploying 74xxx. You formulate your system in VHDL, Verilog or Matlab and that's it. Nobody cares about flipflops, let alone their reset pin polarity.
As it happens, I needed more space in may parts store last week and I decided to move most things with pins, 74xx, 10K, 100K etc into plastic containers in the basement. I did not use them in years. Even the rests of glue logic in my designs go into a Coolrunner2.
7400 TTL convention, perhaps to reduce power dissipation due to an infrequently-used function. 4000-series CMOS usually used active high IIRC.
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Phil Hobbs
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The basic gate in early DTL and TTL logic was the NAND. It was faster and more economical to make a master-slave flipflop with additional NAND inputs for preset and clear; active low over-rides into the main bistable. Hence the 7474 type flipflop.
The basic RTL gate was a NOR, so RTL flops usually had active-high preset and clear.
TTL killed DTL killed RTL, so TTL won. CMOS inherited the TTL conventions.
They work, at least for the most part. The unused input treatment seems iffy but I just tie them to a logic level.
Haven't used ECL-style in more than a decade, mostly because they are too power-hungry and power consumption matters more and mre these days. Even on airliners they cound every drop of kerosene and thus watts in the electronics.
I did yard work yesterday, maybe it was in the upper 80's. Having lived here for so long plus some Arizona exposure, I don't notice heat much. When I ride a bicycle full bore on a 105F day people think that's crazy. You just need enough water and an empty yoghurt beker to dump water over the T-shirt.
"Perfectly" depends on how far one has to go with parameters such as input capacitances. I don't think those are part of an LTSpice simulation. Would need a full non-behavioral model.
Long in the tooth - retro, same thing :-)
Old TTL didn't pull very high. 3.5V to 4V in some cases so noise immunity was indeed worse, until CMOS came. That made things cumbersome because you could not use OC structures to operate it from external.
Nobody? Really nobody? Way north in France, in the province of the Gauloises ...
For example, right now I have to design a circuit for a device that replaces a uC function because the uC can't be trusted to do the job reliably enough. I think it could be made reliable but a client's wish is a client's wish. It'll need several 74LVC chips.
My designs are often cost sensitive, mass production, where programmable logic is too expensive. A 20c Coolrunner could work, 50c would not.
Storing parts farther away has health benefits. In my office the book shelf is 5ft from my desk so I have to get up from the chair every time. Transistors are in the room next door from my lab bench so a short walk is required. It's healthy. I saw a neighbor yesterday who stopped retirement for another engineering job. Despite diet cutbacks he has developed a profound belly, not very healthy. It'll easily take more than a year to get rid of that.
TTL levels have nothing to do with 5V. That is just the supply voltage. The switching threshold is somewhere near 1V8, anything below 0V6 is definitely low and anything above 2V4 is definitely high.
CMOS has its threshold at 1/2 VCC, but the historic importance of TTL required the extraneous 74HCT family with the lower TTL input threshold, implemented by playing games with the width/length ratio of the FETs.
Deploying a few gates is not digital design.
Consultant's creed: It's our policy to give the customer what he wants. That is very strong medicine, and usually only required once.
And sometimes the drive signal didn't quite get there. Or not all the time. The threshold in TTL is lower though, but occasionally it wasn't low enough. Unless you used 244 bus drivers this stuff just didn't have any oomph.
That is one reason I was never much of a fan of HCT. In my youth I built a lot of circuits with CD4000 logic because it didn't have such problems. It had other problems but the main upside was a vastly lower power consumption.
That part fulfills logic funtions. If this and that happens at the same time tug on an alert rail, otherwise not. Preferably while consuming less than 1uA. What's not digital about that?
:-)
Once is the goal, of course. After that I (and the client) expect this to run for the next few decades.
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