Xilinx DDR2 SDRAM controller performance

Which MIG version are you using? Xilinx changed the controller algorithm between versions 1.6 and 1.7 of MIG.

In a Xilinx webcast on the MIG DDR2, they explained that one of the areas that people may want to modify is the bank switching algorithm, as their controller can only maintain a limited number of banks open at a time. This will probably have an impact on your random access performance.

Have you compared the bus utilisation with that when you write contiguous blocks? That way, you will know for definite if that is your issue.

Andrew

Hi Andrew, thanks for your response.

I'm using MIG version 1.7. I have modified the contoller code to fix a bug where the MULTI_BANK_EN is incorrectly being defined as an integer 1. This is now defined as 1b'1. Before I did that the controller would issue a new active command even when the next access was to a bank/row that was already open.

I have run a test where all of my accesses are to the same bank and row. The test would write 128 bytes (toggling only col address bits) read it back, write another 128 bytes, read it back, and so on. This test achieved 51% data bus utilization. If I did a similar test where only bank address bits toggled I could sustain 41% utilization. Neither of these scenarios are very practical, but it tells me that even under the best conditions the bus is idle half the time.

If I only read, or only write, than the controller can come close to

-Bruce

I suppose this has to do with transaction pipelining and ordering. In theory you can setup a read or write access in another bank so it commences right after finishing the current bank. This make the controller a lot more complex. Don't forget the MIG tool is a demonstrator!