Hello! Everybody
I got a double port RAM from Xilinx IP core generater. I test it. There is always one warning : No primary, secondary unit in the file "D:/FPGA/testram/testram/ram1.vhd. Ignore this file from project file "testram_vhdl.prj". I don't know what is it? Does any nice people tell me the reason. I got the vhdl function model of this block ram from IP core generater.
---------------------------------------- LIBRARY ieee; USE ieee.std_logic_1164.ALL;
Library XilinxCoreLib; ENTITY ram1 IS port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); END ram1;
ARCHITECTURE ram1_a OF ram1 IS
component wrapped_ram1 port ( addra: IN std_logic_VECTOR(2 downto 0); addrb: IN std_logic_VECTOR(2 downto 0); clka: IN std_logic; clkb: IN std_logic; dina: IN std_logic_VECTOR(7 downto 0); doutb: OUT std_logic_VECTOR(7 downto 0); wea: IN std_logic); end component;
-- Configuration specification for all : wrapped_ram1 use entity XilinxCoreLib.blkmemdp_v6_1(behavioral) generic map( c_reg_inputsb => 0, c_reg_inputsa => 0, c_has_ndb => 0, c_has_nda => 0, c_ytop_addr => "1024", c_has_rfdb => 0, c_has_rfda => 0, c_ywea_is_high => 1, c_yena_is_high => 1, c_yclka_is_rising => 1, c_yhierarchy => "hierarchy1", c_ysinita_is_high => 1, c_ybottom_addr => "0", c_width_b => 8, c_width_a => 8, c_sinita_value => "0", c_sinitb_value => "0", c_limit_data_pitch => 18, c_write_modeb => 0, c_write_modea => 0, c_has_rdyb => 0, c_yuse_single_primitive => 0, c_has_rdya => 0, c_addra_width => 3, c_addrb_width => 3, c_has_limit_data_pitch => 0, c_default_data => "0", c_pipe_stages_b => 0, c_yweb_is_high => 1, c_yenb_is_high => 1, c_pipe_stages_a => 0, c_yclkb_is_rising => 1, c_yydisable_warnings => 1, c_enable_rlocs => 0, c_ysinitb_is_high => 1, c_has_default_data => 1, c_has_web => 0, c_has_sinitb => 0, c_has_wea => 1, c_has_sinita => 0, c_has_dinb => 0, c_has_dina => 1, c_ymake_bmm => 0, c_has_enb => 0, c_has_ena => 0, c_depth_b => 8, c_mem_init_file => "mif_file_16_1", c_depth_a => 8, c_has_doutb => 1, c_has_douta => 0, c_yprimitive_type => "16kx1"); BEGIN
U0 : wrapped_ram1 port map ( addra => addra, addrb => addrb, clka => clka, clkb => clkb, dina => dina, doutb => doutb, wea => wea); END ram1_a;
-- synopsys translate_on