Virtex6 Virtex4 FPGA compatibility

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I happened to notice one thing, Virtex6 does not support 3.3V I/O. Barry

S. Bernstein schrieb:

Virtex6 and Virtex4 are not pin-compatible, as far as I know, so the board will have to change. Plus, core voltage is different for the two families, so the power supply will have to be adjusted. Plus, as another poster noted, there is no more 3.3V-IO, which might be a problem for you as well if you need it. I'm sure there's a lot more subtle differences...

cu, Sean

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Anyone know if 3.3 volt I/O is still with us in the new Spartan 6 devices?

Rick

http://www.xil> Multi-voltage, multi-standard SelectIO banks

So yes - hurrah!

Any bets on whether the next Spartan family will still have it?

Cheers, Martin

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

I would say that depends on when it comes out. I don't see any sign of the 3.3 volt standard going away any time soon. So over the next five years, any FPGA aimed at the general logic market will pretty much *have* to support 3.3 volts. As the feature sizes shrink we hear that (at least in the case of Xilinx) it becomes prohibitively expensive to continue to support higher voltage I/O standards. Although the semi companies that are making parts that aren't FPGAs still seem to manage to support 5 volt tolerant I/Os, I guess at some point this really is true.

It is just a matter of where your market is. The FPGA vendors have decided that the market for 5 volt tolerance is not worth the extra per part cost. They trade off the design wins they miss out on because of price vs. the ones they lose on I/O voltages. That is why the Spartan and the Virtex lines have diverged at this point. The high end stuff does not use as much 3.3 volt TTL I/O as it demands high speed serial and LVDS. Spartan is aimed at a different market that still demands a lot of 3.3 volt I/O without adding expensive and bulky interface chips. At some point even the 3.3 volt I/Os will become a liability and the low cost product lines will drop support.

I think it is especially interesting that Lattice has dropped their pursuit of the high end market. I am sure that X and A will spin this as L not being able to keep up with the big boys. But there is also the dynamics of the FPGA market. It may well be that the high end is not where the future is. They may make $500 per 1500 pin/ 10,000,000 gate FPGA, but how many can they sell? On the other hand, if they can cost effectively get an FPGA into a digital camera they only need to make a buck per chip to make millions. Right now, in the cellular market, they are pretty much limited to the low quantity base stations. If they can ever get a seat at the cell *phone* table, then the sky is the limit! And they might not need 3.3 volt compatibility to do that...

Rick

Not so fast. Listing 3.3v I/O and having it usable in the real world are not the same thing. You need to check how much allowance there is for overshoot, which will determine how perfect your impedance match needs to be to be able to use 3.3v I/O in the real world. I don't know about the part in question, but for some recent fab processes there hasn't been much in the way of safety margin.

All,

The fabs will make anything you want. If you want a 5V IO, that is what you get.

The market (and here I mean where the money is) wants very fast DDR3 interfaces. To do this one requires 180nm IO transistors (optimally), or 250nm IO transistors.

That means 1.8v IO or 2.5v IO.

So, for a FPGA, one must choose the highest performance you need, and that will constrain your highest voltage options (unless you decide to have more than one oxide for IO, which greatly increases cost, and design complexity, decisions as to what to provide, and thus time to market).

So, Xilinx doesn't decide to 'drop' 3.3v. The V6 doesn't support 3.3v IO like in previous families, but S6 does. The customers told us quite clearly what was required, for their dollars (yen, NT$, euros, pounds, etc.).

As for 'safety margin' it is true that more aggressive process means perhaps less tolerance to overshoot and undershoot. Hopefully, the recommended operating levels in the specifications are clear, and good signal engineering practices are followed. If you don't care about SI, then you are likely to have other problems, so it isn't such a big deal anymore.

Austin

rickman wrote: (snip)

Even for the original TTL, logic high was just 2.0 volts. For an output, you only need to get up to 2.0. For inputs, many Xilinx families will do it with a current limiting resistor such that the protection diodes aren't overdriven. I suppose one could add external diodes for extra protection.

For tristate (bidirectional) I/O, though, the resistor approach probably won't work. An external protection diode might, though.

As far as I understand it, the thicker oxide for higher voltage results in slower transistors. You can have speed or volts, but not both.

-- glen

That reminds me of the initial versions of the Spartan 3 which had

*very* tight specs on over and undershoot. The eventually relaxed it a bit as a lot of people screamed about it... at least they did here. Hopefully that lesson has been learned.

Rick

Well that's true, but at least the possibility of engineering it right exists :)

Cheers, Martin,

--
martin.j.thompson@trw.com 
TRW Conekt - Consultancy in Engineering, Knowledge and Technology
http://www.conekt.net/electronics.html

The question is what is 3.3v support. For example in CycloneIII the

3.3v IO is almost unusable for any fast signal, the maximum drive strength is so low. Fortunately if 3.0v is used the drive strength is better, and 3.0v should be compatible enough with 3.3v standards.

--Kim

At the cost of an additional voltage.

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Uwe Bonnes                bon@elektron.ikp.physik.tu-darmstadt.de

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