Virtex-II Pro DDR Memory Controller

I've been working on a DDR SDRAM controller for a Virtex-II Pro 7 (ff896 package, speed grade 5) So far I've tried the controller from OpenCores, and looked at some of the app notes from Xilinx. I was looking at App Note 253 in particular, but someone on the Xilinx forums said that he had only been able to get it work with the test bench, not in the real world yet. This is the same problem I spent about 3 weeks on for the OpenCores controller. I am using the Avnet evaluation board, which has 2 Micron mt46v16m16 chips, with

16 data lines each. All lines are common between the two except for DM, DQS, CS#, CLK/CLK#, and data. The data interface to the FPGA is 32 bits wide (16 from each chip). Can anyone suggest what app note, or other free IP, would be the best place to start? For this project, we want our custom logic talking directly to the memory controller, and probally will not be using the on-chip PowerPC. I've looked at modifing the DDR control from the Xilinx EDK, but someone in the Embedded Processing Division told me it would be easier to make a state machine to "fake" the OPB bus signaling. Is that actaully the best way for me to go, or is there something simpler?

Thanks, Mike

package, speed grade 5)

app notes from Xilinx. I was looking at App Note 253 in particular, but someone on the Xilinx forums said that he had only been able to get it work with the test bench, not in the real world yet. This is the same problem I spent about 3 weeks on for the OpenCores controller.

chips, with 16 data lines each. All lines are common between the two except for DM, DQS, CS#, CLK/CLK#, and data. The data interface to the FPGA is 32 bits wide (16 from each chip).

place to start? For this project, we want our custom logic talking directly to the memory controller, and probally will not be using the on-chip PowerPC. I've looked at modifing the DDR control from the Xilinx EDK, but someone in the Embedded Processing Division told me it would be easier to make a state machine to "fake" the OPB bus signaling. Is that actaully the best way for me to go, or is there something simpler?

There possible isnt such thing you are looking for :( that is anything that can be found either does not work "out of box" or needs to be modified heavily. I found the same thing to be true for SDR SDRAM as well. Ended (ending) up almost rewriting from scratch.

For you - get an working EDK design for your board, get it working, attach chipscope the DDR io's make some snapshots - then start with some core you are going to use for your own purposes and at each step try to compare whats different (if your modified core doesnt work). Sure you can achive something with pure simulations also, but in any case you are looking at some week worth of time to get your custom DDR core working in FPGA (that my thumb estimate, if you are very lucky can maybe stretch a few days)

Antti