There is a netlist synthesied, say, for an ASIC technology. The netlist should be prototyped on FPGA. Therefore, it should be implemented by FPGA vendor's tools. Implementation should be done automatically for any netlist given in EDIF format. Functionality of primitives is known. One of the solutions is to create a VHDL netlist and resynthesize. It would be possible to bypass VHDL export and synthesis by building (on-the-fly) a macro-library of the ASIC primitives out of vendor's primitives, specifically out of Xilinx's UniSim primitives. Please, give the idea, what are the macro-libs and how can they be created? Thanks.
- posted
20 years ago