Hello all, anybody knows how can I extract equations from Xilinx schematic? I tried in Schematic Editor: Option->ExportNetlist and VHD file has been generated...but to get clear equations (Out=f(In)) I must translate whole of file...
Maybe somhere is tool for extracting euations from VHDL file?
Regards Kuba
It sounds like you want a "de-compiler" What you get from the schematics is structural VHDL describing the library modules and their connections from the netlist. You would need a tool that understood the functions of the library primitives and converted the instances into code that infers the same function. I've never seen anything like that.
"buke2" wrote in news:ce7m97$16g$ snipped-for-privacy@nemesis.news.tpi.pl:
I know that the report file for a Xilinx CPLD lists the Boolean equations for the various outputs. If you don't have any FPGA-specific macros in your design, then you might be able to retarget for a CPLD just to get the equations.
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