need small PAL with SR latch

The Xilinx SpartanXL had RS latch options in the CLBs, but it wasn't well supported. RS latches tend to cause timing headaches and aren't recommended. If you insist on RS latches the tools will infer one from VHDL, though will bitch loudly (at least Synplify would do both).

Hi Colin,

Some (possibly even most) parts have the ability to route the AND-OR array output back to the input side of the array again prior to the output block (typically this is used when they need to use more product terms than a single block can provide), and hence the loading of the output pin has essentially zero effect.

Hi, I need a small prgramable logic device with a couple of SR latches, however they all seem to have D types or other type of latch on the macro cell with a global clock/set/reset, exept for some of the realy big ones.

Ive looked through all of the ones that Farnell sell, and although I could obviously feed back an output to make an SR latch this wouldnt be ideal, any one know if there are any like this ?

Only needs a dozen gates or so to do the job, could do with being fast as posible and in circuit programable etc.

Colin =^.^=

macro

ones.

isn't

staightforward

array

I estimate there would be 6 gates in the circular path as well as the loading of the output pin and grid lines, compared to a normal latch etc were there is a circular path of 2 gates with minimal loading. there would be a significant diference in speed/generated noise. Im trying to acuratly measure relative edge timings so the faster the better, bit like in a type II phase detector, except I found that doesnt work quite the way I expected as it is indeterminate if a waveforem is 90' or 270' out of phase. a simple xor detector would not alow as much sensitivity.

fast

amazed

I havent designed in any pld's for ages :)

Colin =^.^=

Hello Colin,

I have designed out a lot of PLD for ages. Usually because they were expensive power hogs ;-)

Regards, Joerg

what sort of devices did you replace them with ?

Colin =^.^=

Hello Colin,

Mostly with logic. In TSSOP the total real estate usually didn't grow but the cost was substantially lower. Plus the stuff didn't become obsolete a few years later.

Sometimes the replacement was a cheap uC, other times a small LUT ROM.

Regards, Joerg

aha i see,

all i need is 1 nor, 1 nand, 1 sr latch, 2 xor, and a 1 bit tri state buffer, I could probably do it with a very fast LUT too but im not sure if u can feedback data lines to address lines reliably unless its clocked, otherwise thats a few diferent packages even if i try and convert some of the gates etc.

A gal16v8z doesnt seem to consume much power unless they are hiding it well in the data sheet, oh wait thats in standby, at 10mhz its 55ma but im not pumping the clock line so maybe itl be a lot lower.

Colin =^.^=

Hello Colin,

Look at "Normalized Icc versus Freq" in the lattice data sheet on page

1. It doesn't exactly appear to be a static CMOS behavior, there is a pretty stiff pedestal at 0MHz.

What really irks me and is acutally often the main reason why I do not use GALs in my designs is the cost. Your 16V8Z, for example, gobbles a whopping three to four (!) Dollars per chip. No thanks. I can do that with logic for 50 Cents or so and chances are pretty good that my clients can buy exactly those same logic chips 15 years from now without any problems. From half a dozen sources.

Regards, Joerg

if u

of

well

not

yes there seems to be lots of difernt parts of the same sort, maybe they would be cheaper otherwise, or if you didnt keep designing them out HA ! the cheapest I found was 70p @ qty 100

Maybe it has an internal clock running for some reason ? bias generator perhaps ?

I wonder if the lattice software predicts supply curent im just tryin to get to grips with that softwar enow.

Colin =^.^=

Hello Colin,

If that is 70 Pence (UK) I'd still consider that expensive.

Maybe but when something gets warm without doing much I don't like to design it in.

I was always a bit afraid that someday an assembly house messes up PAL placement. Others (the PAL aficionados) told me that I am too paranoid about that. Then came that day. Almost 100 boards totally non-functional because they had slipped a number on the SMT placement. The boss there almost went ballistic.

Regards, Joerg

For a 22v10 sort of architecture, an RS latch is just

Q = Q * \\CLR + SET

which is just one macrocell.

John

macro

ones.

fast

thanks,

Im trying to get to grips with some of the software from the manafacturers, I tried Altera's Quartus II and that seems realy nice and easy to use, and has no trouble taking my schematic with an rs latch. however they only do devices many times larger than what i need. with about 100 too many pins!

I tried Lattice and finding this awkward to use but managed to create a schematic with an rs latch, I was puzzled becuase I couldnt relate this to the data sheet, however I realise now this isnt what I need as it is using a D type latch (with a clock wich i had ignored), so I reverted to using 2 gates to do the RS latch function.

Im confused though becuase it seems to have created a gal16v8 but with what apears on the chip report to be negative logic outputs wich isnt what i asked for or want.

maybe it would be better to enter it in vhdl ? what would be an ordinary rs latch as oposed to a equivalent of a clocked D type latch?

Colin =^.^=

You can easily do an RS latch in a GAL16V8 in CUPL it would look something like this :

q=q & !reset # set;

latches,

hi thanks, I managed to get into VHDL and found it reduced my logic a bit and warned about what apeared to be part of the q node. so I re wrote my logic to match what was created ...

Yeow! I have no experience with Altera, but it sounds like you have something seriously wrong with the setup.

The D-flops often have both Sets and Resets, but often they can't be connected into the routing matrix, or only one can at a time. You are asking to do something that the manufacturers try to prevent you from doing. I had similar problems trying to make a D-type latch. While the two gates should work, the problem is trying to convince the software that this really is what you want. It will try to prevent you from doing it.

I'm confused. You asked for a 16V8, or it chose for you? You may have IOB issues as well. Getting the IOB right can be a PITA.

Perhaps something like... (r,s, and q are standard_logic or standard_ulogic)

SRLatch: Process (S,R) -- Set dominant SR latch BEGIN IF s = '1' -- Set is dominant THEN q

Oh, *now* the light goes on. I thought your design came out with 100 pins. Yes, FPGAs are going to have a lot of pins. ;-)

Not necessarily more idiot-proof, but clocked logic can be simulated and timed. Asynchronous logic and loops in logic are nightmares.

;-)

It will. You can instantiate devices directly, much like a text version of a schematic. You need to know what is in the library though. I try not to do this because it messes up the VHDL and makes it less portable. When I find it necessary, I keep all such instantiations in seperate files and mark them as being technology dependent.

If R and S are low, neither IF clause is triggered and the data is whatever it was. If either is active that clause is triggered and the appropriate THEN is executed. One key point here is the sensitivity list in the process statement "(s,r)". This triggers the process to be evaluated whenever R or S changes state.

I found VHDL, at least the synthesizable subset, to be very easy to learn. Much of the difficulty is in knowing what synghesis is going to do with your source code. Synthesis matches templates, so your job, should you choose to accept, ;-) is to learn what templates turn out what logic.

latches,

although I

be

manafacturers,

and

do

pins!

I think its just simply that the smaller Altera devices are listed as 'classic' so I gues they dont do them anymore, the software for them 'Max plus II' is listed as superceded by the new software but that lists the smallest device as having nearly 100 pins.

Yes I am getting the hint now that they dont want you to do something like this, I gues they feel clocked logic is more idiot proof, and that were all idiots or something and timing issues are to hard for us to sort out ... as it was I now realise the RS latch I thought I had selected was not the simple type i was after but a clocked version (ie synchrounous set/reset) and as I had tied the clock to VCC it kindly reduced it to nothing.

Confusion abounds ... The lattice software asks you to select either 16v8,18v8 or 22v10 etc If I select a gal22v10 it comes out correct but not if I select 16v8,20v8 etc. Im not sure what i need to do in relation to the IOB for the 16v8 that I didnt have to with the 22v10 ? I just let it chose the pin assignments. I also find that the OE wich can be 1 product term from the matrix is not able to cope with more terms, even if I asign the equation (a xor b) to another pin it still tries to use the 2 terms necessary to do the xor rather then use the term already generated, wich is a bit frustrating. Is there another software package that would be better than the one lattice provide ?

Ah thanks, I was thinking that VHDL would alow you to enter devices from a library (like you would on a net list) but obviously not. So the compiler makes sure q doesnt change if s and r are low I gues ? I wil give it a try :) At least now ive got started in VHDL ...

Colin =^.^=

Crap. I've never had enough pins. Even an FG680 ran out of pins (five years ago).

It's not just "easy" it's "possible".

Actually, no they don't. You have no idea whether your routing this time is the same as last. Metastapility is a horrid thing when you have no clue what your feedback time is. That's just one of the heads of the FPGA hydra.

Not so, grasshopper. It's not even possible to know. All you're doing is opening the window of death. ...and not knowing how wide!

Naw. We haven't gotten there yet. Clocks are still distributed in a sane manner and even taken care of in the timing analysis. ...you add your loops, and all bets are off!

The may be, but I doubt it. As Iv'e said, these are an anethma to logic design. ...not to mention test.

VHDL *is* essentially a multi-threadded language. The point of the PROCESS statement is to serialise execution. The last to set a signal/variable in a process rules though (bottom to top, as it were).