Hi,
Is the locked signal of DCM, is synchronous / Asynchronous ?
Regards, Muthu
XILINX FPGA: DCM locked Signal
Dec 05, 2003
3 Replies
Muthu,
It is generated on the rising edge of CLKIN -- synchronous.
Aust> Hi,
So is possible the situation desscribed below ?
- the DCM is locked on an input clock;
- I stop completly the clock (from outside the FPGA),
- the DLL looses lock, but the LOCKED signal is never updated and remain high
I think I observed something like that. If it is correct, it's a disturbing feature.
Tullio
Tullio,
That is what the status bit "CLK_IN_STOPPED" is for.
Aust> So is possible the situation desscribed below ?
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