Hi there, I'm having a bit of confusion using arrays in VHDL.
I know I can:
type heap is array (0 to 800) of std_logic; signal que: heap; ... que(0)
Hi there, I'm having a bit of confusion using arrays in VHDL.
I know I can:
type heap is array (0 to 800) of std_logic; signal que: heap; ... que(0)
what about
Jochen
Thanks, I'll have a read through it. I did search for the answer to my problems via google - my apologies if i've asked a really simple question.
Ta anyway :)
my
Howdy Alan,
Don't forget to search in groups.google.com... I found several discussions on strings (which probably aren't what you think they are), good VHDL books, and arrays - mostly in comp.lang.vhdl.
To answer your "compiler" question, if the schematic tool generates moderately decent VHDL, then most synthesis tools (which is our term for compiler) will generate decent stuff. The last schematic tool I used was one made by Mentor (before it changed its name several times [the tool, not Mentor]). I was pretty happy with its output, but I'm sure it is way out of your price range. You can search in google.groups.com for more dicussion on this as well (in comp.arch.fpga).
BTW, from the wording of your original question (especially the que(0)='a' part), it seems like you are approaching VHDL as a typical programming language. You know that it is not, right? When coding in an HDL (either VHDL or Verilog), you have to think in terms of the physical hardware you want (FF's, memories, counters, shift registers, and individual bits being OR'ed or AND'ed together).
Have fun,
Marc
Yeah, I'm trying very hard to visualise how the statements I make will map to hardware. Finding it kind of hard though, so I'm hoping some nice books will help me out. Ta for the searching-google-groups tip, btw!
So are schematics compiled to VHDL which is then synthesised? I always assumed the HDL was 'compiled' into a schematic which was then mapped into the chip.
I'm determined to master this fpga marlarkey.. even if it takes me a log time.. :) Thanks.
-Alan
will
Howdy Alan,
Until you have the hardware drawn (in your head, on paper, or in a schematic tool), I dare say there is little chance of getting the desired result(s) out of the tools. I'm not saying this to make it sound difficult or to keep you from trying - just that even people who know what hardware they want find it easy to screw up HDL's.
always
The Mentor schematic tool created VHDL. I don't know if Xilinx's schematic tool does or not - but it wouldn't have to. It could directly synthesize the schematic into a netlist, if that's how they designed it.
If you have some digital design experience, it shouldn't take too long to get a fair understanding of it.
Good luck,
Marc
que'1'); que(0 to 7)
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