I would like to use the "locked" output of a DLL to make sure that my internal logic (ie. FSMs) doesn't start-up until a stable system clock is available.
I'm not sure if the "locked" signal is already a synchronous one, or if I better use a 2-stage synchronizing circuit to move it to my system-clock domain. Anyone knows ?
Many thanks, Guy.
Guy,
LOCKED is an output from the state machine which is clocked by CLKIN.
That makes it synchronous. It must follow (shortly) after a rising CLKIN edge.
PSDONE is from the phase shift state machine, so that output is synchronous to that clock. If PSCLK and CLKIN are from the same source, then that solves that.
Aust> I would like to use the "locked" output of a DLL to make sure that my
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