I am doing a small experiment with DCM. I used the coregen to configure it to use a 100Mhz input clock, and output CLK0 and LOCKED. RST is also tied to a pushbutton RESET. Feedback 1x internal is configured, and so does the duty cycle correction. Then I instantiate the module in schematic, and tie all the port to inport and outport apprepriately without any IBUF,OBUF or BUFG primitives. I noticed a extra pin coming out of the DCM: CLKIN_IBUFG_OUT. I implemented the design and downloaded to a xc2vp4 FPGA prototype board. But somehow I can not get CLK0 to come out. CLKIN_IBUFG_OUT is coming out fine. LOCKED is still low. So it is not locking, and that is why CLKO is not coming out. But why? Such a simple design. Someone help.
Charles