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Using the Virtex Block Select RAM+ Features

Hello,

there is an application note from Xilinx: XAPP130 (v1.4)

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On page 4 there is table 3: Port Address Mapping.

There are some formulas given for Start and End.

My question: What do Start and End mean? What is the meaning of ADDRport(Read or Write?)? What is the meaning of Widthport(Read or Write?)?

Maybe someone can it explain on some example:

write port data width[0..0] write address [14..0]

read port data width [9..0] read address [31 ..0]

How can the formulas be applied to this example?

Thank you for your help.

Kind regards

Andres Vazquez G&D System Development

Reply to
Vazquez
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Tehe address mapping is only of concern when you use different aspect ratios ( depth x width) for the two ports.

You may want to read XAPP463 which, for Spartan3, describes the same BlockRAM as in Virtex-II and Virtex-IIPro. But this description is younger and better.

For each port, you can chose between 16K x 1 (deep and narrow),all the way to 512 x 36 (shallow and wide ). The table shows you the mapp>

Reply to
Peter Alfke

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