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dual port RAM - write cycle problems

Hello,

I use the Sapartan-IIE from Xilinx. In my application I'm writing with an µC to the dual port block RAM of the FPGA. If I'm writing only once to the dual port RAM, I succeed. If I write several times to the RAM it get's confusing. The error is not the same all the time. It differs. I attempt to write 32 bit values to the dual port RAM. To see the result, I read out data from the second port. I use a 7 segment LED the display the results. The addresses of the second port are input be DIP switches. The second port is only read (enable pin active all the time; read/write line permanently set to READ). And that's my test software: The first value is written to adress 0x0 of the dual port RAM. The second value to adress 0x1 (and so on...) The first port, I use for the interface with the µC, is actually configured as a 32 Bit port (generated by the CoreGenerator from Xilinx ISE 6.1.01i)

And that's the result: Sometimes the first write cycle of the µC seems o write data to address 0x1 of the block RAM and with the second write cycle data seems to be written to address 0x0. Data seems to get interchanged. Sometimes it seems that in address 0x0 there are no reasonable values at all (Nothing that could have been written by the first or second write cycle of the µC; but data at address 0x1 is correct). Writing 4 times to the dual port RAM can result in various errors. Sometimes the values seem to be shifted through. This means: data values that are written to adress 0x0 are found at adress 0x1; data written to adress 0x1 is found at adress 0x2. Data written to adress 0x2 is found at address 0x3. And data written to address 0x3 is found in 0x0. There seems to be a kind of shifting in the dual port RAM.

How can this be? Is there something wrong. I attach the code I use for the write process for the FPGA. Is it possible, that the problem comes from "if rising_edge ..."? Should it be "if IOSTRB_DSP='0' " ? But then the process is not synchron anymore. Isn't it.

WRITE_DSP : process(IOSTRB_DSP) -- Daten schreiben ins RAM (data -> ram) begin if rising_edge(IOSTRB_DSP) then if CS_DSP = '0' and IORW_DSP = '0' then -- IORW=0: WRITE; CS and EN are active low dinb

Reply to
Tobias Möglich
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Tobias,

From this code it is not clear what the timing relationship between the address bus, write enable, clock and your data when they are all applied to the memory. You have to make sure that your address is stable when you do your write. Have you simulated this? Have you looked with a scope or a logic analyzer? Do you have Xilinx Chipscope? I would suggest starting with simulation if you haven't done so yet...

/Mikhail

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Reply to
MM

Consider synching everything to the uC clk.

if rising_edge(clk) then =2E . .

And use IOSTRB_DSP as an input.

-- Mike Treseler

Reply to
Mike Treseler

Thank you for your advice. I tried to use ModelSim Starter XE. But it has not much resources (free version). But now I downloaded ChipScope (free version) and it seems to help !!!

Question: Is it also possible to analyse signals of IO pins. It seems to me that they are not available in the "ChipScope Analyser". Is it so? Or is it a mistake of mine. Yet I couldn't manage to display signals which come directly from a IO pad in the scope

Tobias

Reply to
Tobias Möglich

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