Thank you if you watched the previous story on Virtex-4 performance. Now please click on
and sign up for the next presentation in this series, where Matt Klein of Xilinx Applications will explain the three aspects of power consumption. This is again an engineering presentation: Matt has been a "power user" of Xilinx FPGAs for over 17 years, he even published a Xilinx app note in 1990, while working at hp. We have been friends since 1988, and I was thrilled when he decided to join Xilinx Applications last year.
The previous talk on performance had excellent participation, and a spirited follow-up debate in this newsgroup. Thank you, Paul, for providing spice with the contrary point of view ! I hope many of you will join us again coming Tuesday at noon, Pacific Time.
We have finished our PPT slides and polished the presentation. It will be tutorial and technical in nature, but will also not shy away from competitive issues. I will play host, and Matt Klein will give the presentation. No accent, and hopefully no audio problems... My previous posting indicated the wrong time, it's really at 11:00 am Pacific Time this coming Tuesday, Feb 15. Hope you can join us for this and the subsequent seminars in this series.
Too bad the slides are done given that we've released updated power specs. I'm sure you will carefully caveat the comparison appropriately...
BTW, I sincerely hope you will stop all this nonsense with in-rush "power". Your web site seems to trumpet a big advantage here, but Stratix II does not have any in-rush current (as announced a few weeks back). Never mind that in-rush "power" is meaningless -- in chips that do have an in-rush event, it is just a temporary spike in *current* draw during power up and in no way relates to thermal dissipation or energy requirements of the device. All this spike affects is the minimum supply size from a transient current perspective.
I personally think it was slimy to take what was a conservative minimum power supply size spec and convert it into Watts and pretend it was a power consumption. But I guess that's marketing... Anyway, it is moot given there is no inrush in Stratix II.
Good luck tomorrow. I'm looking forward to a very healthy debate afterwards :-)
Hi you Rottweilers, back into your cages! We have not even started our presentation. and Paul is already playing umpire. We based our evaluations not only on those published numbers that Altera can change at will, if they are prepared to back them up, and to guarantee them. It is, however, just a little strange that their leakage current evaporated the very moment Xilinx announced a seminar about it. Cause and effect ? Marketing jitters?
We also did made extensive real physical measurements, which we will report. And they cannot be prettied up by a press release.
But why don't you all relax and listen what we have to say. There is plenty of space in this newsgroup for a rebuttal, and a re-rebuttal and a re-re-rebuttal. But remember, hot air just makes the current go up. If all this really produces low-static-power 90 nm devices, users should be happy. Peter Alfke, Xilinx
I am an engineer. I do not knowingly put my name on a spec that could lead to system failures. When I say we do not have a power up surge, and that users only need to size their power supply to meet the operating requirements of the chip, I mean it. This is based on the data we have measured over a variety of conditions and ordering for power supply ramp up.
Are you this annoying in real life?
You thought you had a big advantage on this in-rush business (which was overblown anyway). You do not have an advantage here. Get over it and find something else to harp on.
We guarentee all our specs. That is why we start with conservative estimates, and tighten the specs over time. You see this with our static power data. And you see this with our maximum Fmax specs. It is how we do things. This sucks for marketing, but it means our customer designs work.
I can't expect you to stop liberally interpreting our specs. But I think we should all draw the line at questioning whether either company is cooking the numbers.
I have no control over when we release data. But I can assure you that the data collection and analysis was going on long before your seminar announcement -- it is part of our on-going characterization. Now that we have all family members out, we have the data we need to update our specs.
Wow - all I can say, is I am looking forward to the March numbers, and EPE v2.2 !
Point to ponder: Given the real 'hot button' that power has become, and the huge commercial pressure to 'work the numbers', does that mean the margins are being eroded. What happens if the next batch of chips from the foundries (or a different foundry) nudge these finely tuned numbers upwards ?
Will we see power-bin devices, like we now see Speed-Bin ones, or will prices increase as vendors take the yield hit, or will the EPE v2.71.201 simply quietly change the numbers, and designers find they have to enter the date code of the devices as well ? :)
Hey, if we get another 45% next month, I too will be happy :-) Wouldn't count on it though.
Nope. The numbers are still conservative. Just when we don't have data we have to be more conservative than when we've measured oodles of chips.
We publish two sets of data -- Typical and Worst-Case. Typical reflect where the process is targetted. The actual "typical" value for a given lot varies, but the median over all chips we ever ship should be around the typical value. We don't plan on changing our process targets.
The worst-case numbers are much trickier. We need to set them to a limit that we guarentee such that we don't kill our yields and at the same time don't leave too much on the table. That's part of why it takes so long to come up with the worst-case numbers. We have to have a real handle on the process to make the call.
well ? :)
Hopefully none of the above. But only time will tell.
I admit, I had been worried by Altera's press release, which claimed a
47% reduction in static current. Looked like it might severely erode our advantage. Well, I should not have worried. It was just the usual Altera marketing flim-flam. Here are the numbers Altera published for the worst-case 85 degree static power changes.
It really takes creative marketing to interpret this as a 47% reduction. :-(
And here is how an otherwise smart and nice guy like Paul L interprets it:
"Old data was pre-silicon data for many family members. Icc was based
on projections. Turns out the curve is flatter than expected, so smaller devices have more current than expected and larger devices have
much less current. This is even more evident in the new typical numbers:
The power-on glitch is not something you can wish away, or spirit away with processing tricks. It only goes away when the designer really understands the issue, and does something clever and thorough to eliminate the current spike. We did that about 6 years ago, eliminated the spike in Virtex-II and all later FPGA designs (including Spartan-3). So, if Altera says they got rid of it, let's assume that they finally found the right way to design (or redesign) their chips. Welcome to the club of spike eliminators ! What an ugly problem it was... Peter Alfke
There is a 'sort of scope picture' showing startup currents here
does that count ?
Better (closer to the real world) would be scope ramp up _AND_ ramp down on an operating FPGA - from both suppliers, of course :)
- that way they get to choose the design that makes their dynamic operation look the best. [ maybe there is a dV/dT that looks best on inrush too ? ]
Of interest is if the inrush is purely cap modeled (non clamping) or if it is the stalling clamp type, where a current limited supply can freeze at some point up the inrush mountain ( and a fold back supply may be completely the wrong solution ! )
Power supply design is not my forte. But yes, startup currents are complicated and I'm not sure how much I'd trust any one scope shot. What order do you power up the various power supplies on the chip (it changes things)? What temperature/voltage are you testing at? What point on the process curve is the chip under test?
Rate of ramp up in the power supply is a good example -- if you have a supply that can supply infinite current immediately, you *will* see a "spike". But it's likely the result of charging of board caps and chip caps, and if you use a supply with less capacity, it will just take longer to ramp up to full Vcc. Capacitive "spikes" are not really an issue so long as the board/chip powers up to Vcc within the spec'ed ramp time.
Contention-based power-up cannot be overcome with time. If you do not supply the necessary current, Vcc never reaches the proper value and the chip does not power up. This is the type of "in-rush current" I think we're debating here.
It's easy to design around an "in-rush current" by just using the right size power supply.
Getting rid of contention-based start-up currents in the FPGA require that we stage all the various initialization logic the right way, etc. Not rocket science, but there are a number of details to get right.