hi, i have two processes in my vhdl code for my FPGA. the two processes each will generate a signal with the second one lagging around 5ns. problem is, i am told that this 5ns delay might not be from my coding but from the FPGA processing delay.. may i know how do i check for this processing delay? thanks
Hi,
Is it synchronous or asynchronous processes? If they are synchronous you can set up OFFSET OUT constraints which describes the internal delay in the FPGA from the last clocked element in your design to the output pin. Review the static timing report after PAR and you will get the actual internal output delay. If this doesn't work for you please provide some more information.
/Roger
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