Hi, In my project,there's a xilinx IP core. I want to use the synplify7.7 to synthesize it, but there's a warning when synthesize . The warning is : @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound component counter_11 mapped to black box @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound component counter_4 mapped to black box
my project nane is itu656_dec : a decoder for itu 656 video The following code has been used in my project:
component counter_11 port ( Q: OUT std_logic_VECTOR(10 downto 0); CLK: IN std_logic; CE: IN std_logic; ACLR: IN std_logic); end component;
component counter_4 port ( Q: OUT std_logic_VECTOR(3 downto 0); CLK: IN std_logic; CE: IN std_logic; ACLR: IN std_logic); end component;
Can anybody help me? Give me some suggestion to deal with this kind of warning. You'd better send me some document of how to using xilinx ip core and hwo to synthesize it with synplify. Thank's a lot!!! willie CHEN