How to synthesize the xilinx ip core?

Hi, In my project,there's a xilinx IP core. I want to use the synplify7.7 to synthesize it, but there's a warning when synthesize . The warning is : @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":29:10:29:19|Unbound component counter_11 mapped to black box @W: CD280 :"G:\project\itu656_dec\itu656_Decoder.vhd":37:10:37:18|Unbound component counter_4 mapped to black box

my project nane is itu656_dec : a decoder for itu 656 video The following code has been used in my project:

component counter_11 port ( Q: OUT std_logic_VECTOR(10 downto 0); CLK: IN std_logic; CE: IN std_logic; ACLR: IN std_logic); end component;

component counter_4 port ( Q: OUT std_logic_VECTOR(3 downto 0); CLK: IN std_logic; CE: IN std_logic; ACLR: IN std_logic); end component;

Can anybody help me? Give me some suggestion to deal with this kind of warning. You'd better send me some document of how to using xilinx ip core and hwo to synthesize it with synplify. Thank's a lot!!! willie CHEN

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willie CHEN
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Hi Willie, please refer to the "core generator guide" document. It explains how to do it. the document is located at YOUR_XILINX_ISE_INSTALLTION_FOLDER \doc\usenglish\books\docs\cgn

good luck, Moti

Reply to

"willie CHEN":

synplify7.7 to=20



"Xilinx-boxes" are synthesized within Xilinx-toolchain, as it seems.

Xilinx: XAPP409 might solve your problem.

I'm not sure if that's really important when using synplify, but reading XILINX: xst.pdf might also make sense.


Jan Bruns


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Jan Bruns


These warnings can be ignored. The netlist (edf, ngo, etc) for the core will be picked up when you run ngdbuild. "-sd" option of ngdbuild may be helpful.

HTH, Jim (remove capital letters)

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Reply to
Jim Wu

Thanks all of you! I had solve the problem. And I had write something about this topic. But I writen it in chinese. Hope it useful for the newbie of EDA like me. You can find the document at :

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newbie in EDA
Willie CHEN
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willie CHEN

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