Hi all, I am a student, and I was trying to convert a .vho file produced by Xilinx Core Generator to a .vhd file so that I can make a standard VHDL project, which I can run in ModelSim Simulator. Can anybody comment/advise on whats the best way to do it? I probably would need to include some Xilinxcore libraries, but I am not too sure.Also, the translate on and translate off things, does that help while simulating??
Thanks, Sourabh
a vho file is already vhdl as you would find if you looked at it. Its just a vhdl representation of the logic which has been produced by your synthesis tool and is meant for simulation so that you can simulate the behavior of your design.
XilinxCoreLib is necessary for simulating xilinx cores. Unisim may also be necessary.
translate on and translate off pragmas are for synthesis of the code, and shouldn't affect simulation.
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