Hi all, I am a student, and I was trying to convert a .vho file produced by Xilinx Core Generator to a .vhd file so that I can make a standard VHDL project, which I can run in ModelSim Simulator. Can anybody comment/advise on whats the best way to do it? I probably would need to include some Xilinxcore libraries, but I am not too sure.Also, the translate on and translate off things, does that help while simulating??
Thanks, Sourabh