HDL simple survey - what do you actually use

I'm trying to decide on which to use for a project as the main default that may
include a number of freelance people.
can you say which of these you actually use (the most)
and have the best skills in
Verilog
systemVerilog
SystemC
VHDL
Other
And if possible what type of work you use it for in general
I dont need to know why you use a particular one - and to avoid
flame wars request you dont explain that.
I'm just trying to get a general feel for what people here use regularly.
TIA
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john 

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john
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john wrote on 1/10/2018 9:17 AM:
I have always intended to learn Verilog as well as I know VHDL, but I've never found a good text book that covers the gotchas of Verilog.
I use VHDL for designing FPGAs.
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Rick C 

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rickman
VHDL, for both synthesis and testbenching. Some Verilog sneaks into my design when vendor-provided IP cores only come that way, but I'm read-only on it.
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Rob Gaddi, Highland Technology -- www.highlandtechnology.com 
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Rob Gaddi
VHDL for RTL (primarily FPGAs but ASIC in the past). VHDL + OSVVM for testbenches.
Reply to
Jim Lewis
Verilog for FPGAs
Reply to
BobH
VHDL, it is a forced requirement for military products.
Weng
Reply to
Weng Tianxiang
The same here. And I don't believe in things like SystemC.
Reply to
already5chosen
Whilst I don't think I am up to commercial work, as the biggest thing I have done is the BabyBaby
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I will say I also only use VHDL.
Dave G4UGM
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David Wade
Well that pretty much nails that issue - VHDL it is. Thank you all for the quick and clean replies.
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john 

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john
Am 11.01.2018 um 14:55 schrieb john:
For HW development I have only used VHDL so far. I personally do not know any Verilog.
Though I have used in a project a couple of years ago SystemC for a hardware simulation system, but I have never encountered anyone using it for actual hardware synthesis.
Greetz,
Sebastian
Reply to
Sebastian Doht
I use Verilog (2005) for synthesis and Verilog/SystemVerilog for sim. I'd use more SystemVerilog for synthesis but my cores have to work in a lot of synthesis tools that don't support modern constructs. Currently I'm doing mostly error correction. The state of synthesis tools is still primitive e nough that I have to generate a lot of my HDL using Matlab.
Reply to
Kevin Neilson
I use VHDL, although I can read and do minor work on Verilog.
I mostly do motion control interfaces, but have also worked on some data acquisition systems based on VME boards.
Jon
Reply to
Jon Elson
If you are converting algorithms that were first prototyped in c, then Verilog seems a lot closer. But, there are gotchas related to automatic type conversions that can cause grief. The explicit type conversions in VHDL keep you from forgetting where they are being done.
Jon
Reply to
Jon Elson
Use VHDL as it is required for US military work. There are books with side by side VHDL & Verilog/System Verilog: HDL Programming Fundamentals by Nazeih Botros (VHDL/Verilog) Digital Design & Computer Architecture Harris & Harris (VHDL/SystemVerilog)
Reply to
jim.brakefield
Verilog, Verilog, Verilog.
I've been consulting for over 24 years now and I now focus exclusively on Verilog for a variety of reasons.
I've seen the Verilog vs VHDL discussion many times, it boils down to either a religious or toothpaste debate - what were you raised with or what flavor do you prefer.
I've found I am *much* more productive in Verilog.
At this point, I don't take on jobs in VHDL.
My $0.02.
John P
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john p
I met a guy in another forum who said not only he, but a number of people he has shown to use Verilog at work are much more productive. I've heard that there are various defaults in Verilog that are real gotchas unless you know about them. But no one has been able to point me to a book that describes these issues. Can you suggest a good Verilog book that covers these details? It doesn't have to be a beginner's book as I am pretty experienced in HDL and have even done some work in Verilog. I just want to get to the point that I won't be making student mistakes in my designs. Well, at least no more than I do in VHDL.
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Rick C 

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rickman
Am 10.01.2018 um 15:17 schrieb john:
Is use MyHDL which gets translated into VHDL for synthesis.
Thomas
Reply to
Thomas Heller
The best Verilog reference book that I have found is "Verilog HDL A Guide to Digital Design and Synthesis" by Samir Palnitkar. It is good enough that it lives in my book bag to get hauled to work every day (and shows it now). This is not really a beginners book, and it is not perfect, but it is the best that I have found. There are at least two editions of this out and there may be more. The second edition is the one that is most useful to me.
For syntax questions, Stuart Sutherland's "Verilog HDL Quick Reference Guide" is excellent. This document can be downloaded from Mr Sutherland's web site. I work in Verilog and C depending on the phase of the project that I am in (FPGA or firmware). Swapping between Verilog and C means that looking up the exact syntax is necessary, especially around the transitions.
BobH
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BobH
Do either of these books cover the defaults issue I mention above? I have coded in Verilog by copying from existing work and that has worked pretty well for me. But that was in a day job where I had people I could ask for help if I didn't understand something and it only lasted a few months. To use Verilog on my own I would want to be sure I wasn't embedding any time bombs that would rear its ugly head after the design had been handed off to a customer. Of course, that's always possible from logic errors, but I'm talking about misuse of the language. I'd like a reference book that clearly identifies these potential problems.
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Rick C 

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rickman
I am not sure that there is a quick answer to what you are looking for.
Sutherland's Guide book is extremely short and tightly written (about 48 pages), it is written to provide quick answers on utilizing each language element. While extremely useful, I don't think it will have the answers you are looking for. You can download the whole thing for free from his site:
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and look for yourself. He has several other books including one specifically on "gotchas" in Verilog and System Verilog that I have not read. My start in Verilog was taking Sutherland's class in the late '90s and his class text was clear and well written.
Palnitkar's book has details on usage of Verilog from basic to advanced stuff. One of the main things that I use if for is understanding syntax and behavior of "advanced" language elements from outside sources.
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BobH

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