Hi, I have two problems about the FPGA implementation after I finished my design with Xilinx block set in Matlab.

- What is the relationship between the FPGA clock and the sampling rate which I set up in System Generator when I simulate the system in Matlab?

- When I implement the system in simulink in Matlab, some blocks may have different sampling rate such as one third the input data rate. So how can I achieve this sampling rate ratio in FPGA? Or the FPGA can fullfill that ratio automatically?

Hope someone could give me some ideas. Thank you very much!