System Generator implement to FPGA problem

Hi, I have two problems about the FPGA implementation after I finished my design with Xilinx block set in Matlab.

  1. What is the relationship between the FPGA clock and the sampling rate which I set up in System Generator when I simulate the system in Matlab?

  1. When I implement the system in simulink in Matlab, some blocks may have different sampling rate such as one third the input data rate. So how can I achieve this sampling rate ratio in FPGA? Or the FPGA can fullfill that ratio automatically?

Hope someone could give me some ideas. Thank you very much!

Reply to
Loading thread data ...
1) The sample period is 1/clock rate. If you put the sample period as 10 ns in the System Generator token, you should provide a 100 MHz clock to the design generated by Sysgen.

2) The generated design will automatically implement the different sampling rates that appear in the Simulink model. This is done by using the CE (clock enable) pin on devices within the generated model. As long as the design successfully generates, the generated model will have taken care of sample rate changing.

Reply to

ElectronDepot website is not affiliated with any of the manufacturers or service providers discussed here. All logos and trade names are the property of their respective owners.