Best tool(s) for filter float->fixed->VHDL flow?

I've got a minor DSP/comm task to put in an FPGA:

Complex demod to baseband, CIC+decimate+FIR LPF chain, magnitude estimate, some FSK and DPSK data to interpolate, correlate and extract, plus other sundry tasks.

I'd like to model this all in untimed/behavioral floating-point, have a quick way to evaluate filtering options (including IIR, varying lengths and structures/forms) and quantization effects, with automatic conversion to a somewhat optimal fixed-point implementation that a tool can automatically write out as VHDL (RTL, not behavioral). Parameterizable block diagram entry is a plus. Probes/sinks with FFT and time plots and file writes at nodes of interest are also desireable. (SUMMARY: design/analyze at high level, let tools do dirty, low-level work.)

Maybe I ask too much ;-) but it seems like this is such a common problem and flow that solutions would abound. However, I've been out of the DSP world for a while, and don't know what the best, cheapest, or most productive tool options are...

What would the gurus of comp.dsp and comp.arch.fpga suggest?

I have access to MathCad, Matlab (with FDAT), Simulink, and possibly LabView (National Instruments?) and (Cocentric System Studio (Synopys) but am not fluent with them.

I've entered the design in Cadence/CoWare's SPW, but am getting frustrated with it -- not as easy to explore different architectures as I had hoped.

I suppose Ptolemy is an option, if the learning curve is not staggering. Agilent has some Ptolemy add-ons for fixed-point analysis and optimization, but they're not free or in my company's budget for this project.

Any and all constructive suggestions are very much appreciated; thanks in advance...

MarkJ

Reply to
Mark
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Do you know the Xilinx extension to Simulink, which is called SystemGenerator?

You can set up a behavioral simulation within Simulink. From this simulation you go to VHDL code just by pressing a button.

I tried it in a small task, and it worked really fine.

Certainly, it will not make the best out of the possibilities VHDL provides - and there's a good chance that it wastes lots of the resources of an FPGA.

But I always ended up with synthesized code which did what it was expected to.

This tool chain is rather new - and will need some time to mature, but even if it won't solve your task completely, it might be a good starting point for evaluation.

Bernhard

Reply to
Bernhard Holzmayer

hi,

The freeware winfilter can generate VHDL code for fir filter (8 or

16-bit) coefficients.

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Regards, Adrian

Mark wrote:

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Reply to
Adrian

Hi,

There is a new toolbox for MATLAB called "Filter Design HDL Coder" that adds the VHDL code generation feature to the filter design tool. As you may know, filter design tool of MATLAB can already convert the floating point cofficents to fix-point and this new tool box gives you the last ring of the chain, the Code Generation. However I think you can only use it with the new MATLAB R14 so if you are using an older version of MATLAB, maybe the whole solution be a bit expensive.

Regards Arash

Reply to
Arash Salarian

I don't work in this area but I have heard of some companies whose technology may interest you

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I've got a minor DSP/comm task to put in an FPGA:

Reply to
David Gelbart

For architectural exploration, take a look at the new behavioral synthesis tools coming on-line. If money is no object, consider Mentor's CatapultC (was PrecisionC).

CatapultC takes an untimed C model and converts it to RTL. You guide the compilation process specifying which for-loops to unroll, which arrays to make memories, etc. The process is fast, and you can quickly compare alternative architectural decisions -- the tool plots a graph of area vs. performance so you can see which decision fits with your application.

Other companies in this space include Forte (Cynthesizer), AccelChip, and Celoxica. If you can't fork out $100K+, consider SPARK. It maps untimed C to RTL. It's not free (as in open-source) and I don't know the license restrictions.

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For parametric designs, take a look at Confluence -- a functional programming language for generating synchronous netlists (outputs Verilog, VHDL, C). It's cheap (GPL) and the language was originally designed for DSP.

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Though the process of mapping floating-point to fixed-point is not automated, you just have to write the conversion algorithm once. Then afterwards, when you change coefficient values, precision, the number of coefficients, or any other parameter, the flow is completely push-button.

-Tom

Reply to
Tom Hawkins

A CIC filter cannot be implemented in floating point. To get it to work it must be done in non-saturating integer math, such as is done using non-saturating two's complement representation. The integer math must wrap around.

Dirk A. Bell

Reply to
Dirk Bell

Hi Mark

Xilinx's System Generator for DSP has been designed to do exactly this. Sysgen will allow you to design your entire system in the Simulink environment where you can use all the sinks/sources available in the Simulink library to analyze your design. The Sysgen gateway blocks handle the conversion from

floating to fixed point, and it is easy to simulate quantization effects and see how the design is affected by using different data/coeff bit widths.

Sysgen comes with libraries that contain DDC, CIC DaFIR, MACCFIR blocks and many other dsp blocks, but it is also easy to build your own library out of lower level blocks. You can easily build custom IIR filters for example, and semi-parallel filters that make the best use of available clock cycles out of adders/shift registers/multipliers etc.

There was some concerns raised about the resulting VHDL that is produced, will it perform as well as hand written VHDL? Well, here is how we approach this problem: First, for most of the sub-components in a design, an optimized netlist will be generated from the Core-Generator tool. These netlists map very efficiently to the fpga architecture and use relative placement constraints to ensure consistent timing behavior. Second, if there is a portion of the design that you feel could be more efficientlly implemented by hand written VHDL or Verilog, then the Sysgen tool provides a method for black boxing this HDL so that it can be incorporated into the larger design.

The appearance of the resulting VHDL may be bloated, but the actual performance is bound more by the max fpga clock rate vs sample rate, and how well you make use of hardware folding and pipelining techniques in your design.

Hope this helps, Elliot

Mark wrote:

Reply to
Elliot Schei

That's a very realistic description. I can verify this from my experience.

Especially, if you're unexperienced with VHDL design, it will save a lot of time and make the result more reliable.

Bernhard

Reply to
Bernhard Holzmayer

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