Free PCI-bridge in VHDL for Spartan-IIE

Free PCI-bridge in VHDL for Spartan-IIE

Somebody knows the implementation of

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Regards. __________________________________________________________________ Torsten Lauter ICQ#: 14492119 Current ICQ status: + More ways to contact me __________________________________________________________________

Reply to
Torsten Lauter
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Torsten,

what do you mean by "Free" ? on the link there is notice

"if interested please contact using a form" - there is no reference to any form or download location or conditions. so what it is all about?

also the website says the ref design uses Spartan III not IIE ?

antti

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Reply to
Antti Lukats

Hi,

Mine isn't going to be free, but . . . I am considering releasing a PCI IP core I have been working on for quite some time, and I am trying to gauge the demand out there for a commercial-grade PCI IP core for personal users. However, the PCI IP core itself probably won't be available for another three months at the earliest (I still need to fix some minor problems, and setup the infrastructure before the release.). The price I am thinking of charging for my PCI IP core is only $100 (USD) as long as the licensee meets the following conditions.

  • The licensee resides within the United States (Don't have to be a US citizen.).
  • The licensee Will agree that the PCI IP core will be used only for non-commercial, non-profit, non-academic research, and personal purposes.
  • The licensee is will agree, sign, and mail back to a license agreement form I will provide.
  • The licensee will pay for the PCI IP core license through an online payment source like PayPal.

This is what my PCI IP core looks like:

  • PCI Local Bus Revision 2.2 compliant.
  • Burst initiator/target access support.
  • 6 Base Address Register (BAR) and Expansion ROM BAR support.
  • Meets 33MHz PCI timings with Spartan-II-5 (Currently, no 66MHz PCI support with any device due to setup time issues . . .).
  • General purpose PCI testbench comes with a PCI arbiter, PCI host bridge emulator, and PCI target device to allow the user to quickly debug their design.
  • The PCI IP core supplied in NGO netlist format (Xilinx's proprietary netlist format.).
  • Nominally supports Xilinx Virtex, Spartan-II, or newer FPGAs.
  • Constraint file supplied for Spartan-II PQ208 and FG456 package, Virtex-E XCV300E BG432 package, Insight Electronics Spartan-II 150 PCI card, and Spartan-II 200 PCI card.
  • Comes with three reference designs (Two similar target only designs and one target/initiator design.).
  • Fully supports Verilog (Reference designs and the PCI testbench are written in Verilog.).
  • Limited VHDL support (No reference designs and PCI testbench. Might do VHDL porting of reference designs and PCI testbench someday, but I won't guarantee that.).
  • Supports ISE WebPACK 3.2 or later (The use of ISE WebPACK 5.1 or later is strongly recommended.).
  • Should work with paid version (non-WebPACK) ISE software, but hasn't been tested.
  • Free Xilinx ISE WebPACK and ModelSim XE-Starter can be used to simulate, synthesize, place & route, and generate a bitstream file.
  • Should work with non-XST synthesis tools, but hasn't been tested.

The PCI IP core will also be available for commercial licensees in NGO netlist format or as Verilog RTL code, but they will cost considerably more than $100 (Especially the Verilog RTL license.). The motivation behind this $100 license is to allow hobbyists to build their own PCI device for about $500 ($275 for Insight Electronics Spartan-II 200 PCI card with a parallel port JTAG cable, $100 for the PCI IP core license, $100 for a printed copy of PCI specification from PCI-SIG, and other miscellaneous costs like shipping cost and sales tax.) without having them to spend too much time designing their own PCI interface. My guess is that there are probably a few hundred people in the United States who will rather license a PCI IP core with testbench for $100 than to do their own or use Opencores.org PCI IP core. I believe this PCI IP core is a great learning vehicle for those who want to learn programmable logic or Verilog, or for use in a student project (The student can concentrate on backend logic rather than the PCI bus.). Let me know if anyone is interesting in this product.

Kevin Brace

Antti Lukats wrote:

Reply to
Kevin Brace

Hi,

Mine isn't going to be free, but . . . I am considering releasing a PCI IP core I have been working on for quite some time, and I am trying to gauge the demand out there for a commercial-grade PCI IP core for personal users. However, the PCI IP core itself probably won't be available for another three months at the earliest (I still need to fix some minor problems, and setup the infrastructure before the release.). The price I am thinking of charging for my PCI IP core is only $100 (USD) as long as the licensee meets the following conditions.

  • The licensee resides within the United States (Don't have to be a US citizen.).
  • The licensee Will agree that the PCI IP core will be used only for non-commercial, non-profit, non-academic research, and personal purposes.
  • The licensee is will agree, sign, and mail back to a license agreement form I will provide.
  • The licensee will pay for the PCI IP core license through an online payment source like PayPal.

This is what my PCI IP core looks like:

  • PCI Local Bus Revision 2.2 compliant.
  • Burst initiator/target access support.
  • 6 Base Address Register (BAR) and Expansion ROM BAR support.
  • Meets 33MHz PCI timings with Spartan-II-5 (Currently, no 66MHz PCI support with any device due to setup time issues . . .).
  • General purpose PCI testbench comes with a PCI arbiter, PCI host bridge emulator, and PCI target device to allow the user to quickly debug their design.
  • The PCI IP core supplied in NGO netlist format (Xilinx's proprietary netlist format.).
  • Nominally supports Xilinx Virtex, Spartan-II, or newer FPGAs.
  • Constraint file supplied for Spartan-II PQ208 and FG456 package, Virtex-E XCV300E BG432 package, Insight Electronics Spartan-II 150 PCI card, and Spartan-II 200 PCI card.
  • Comes with three reference designs (Two similar target only designs and one target/initiator design.).
  • Fully supports Verilog (Reference designs and the PCI testbench are written in Verilog.).
  • Limited VHDL support (No reference designs and PCI testbench. Might do VHDL porting of reference designs and PCI testbench someday, but I won't guarantee that.).
  • Supports ISE WebPACK 3.2 or later (The use of ISE WebPACK 5.1 or later is strongly recommended.).
  • Should work with paid version (non-WebPACK) ISE software, but hasn't been tested.
  • Free Xilinx ISE WebPACK and ModelSim XE-Starter can be used to simulate, synthesize, place & route, and generate a bitstream file.
  • Should work with non-XST synthesis tools, but hasn't been tested.

The PCI IP core will also be available for commercial licensees in NGO netlist format or as Verilog RTL code, but they will cost considerably more than $100 (Especially the Verilog RTL license.). The motivation behind this $100 license is to allow hobbyists to build their own PCI device for about $500 ($275 for Insight Electronics Spartan-II 200 PCI card with a parallel port JTAG cable, $100 for the PCI IP core license, $100 for a printed copy of PCI specification from PCI-SIG, and other miscellaneous costs like shipping cost and sales tax.) without having them to spend too much time designing their own PCI interface. My guess is that there are probably a few hundred people in the United States who will rather license a PCI IP core with testbench for $100 than to do their own or use Opencores.org PCI IP core. I believe this PCI IP core is a great learning vehicle for those who want to learn programmable logic or Verilog, or for use in a student project (The student can concentrate on backend logic rather than the PCI bus.). Let me know if anyone is interesting in this product.

Kevin Brace

Torsten Lauter wrote:

Reply to
Kevin Brace

How can you possibly justify this restriction? You get a chance to explain yourself before the rants arrive, but it'd better be *very* good.

David Brown Norway.

Reply to
David Brown

Hello

You must go on the website and must fill out the form. You get the data per email then. I have gotten the data per email and nothing pays.

Regards

Torsten Lauter

"Antti Lukats" schrieb im Newsbeitrag news:c1di1m$vqs$00$ snipped-for-privacy@news.t-online.com...

Torsten

Reply to
Torsten Lauter

Dear Antti,

the code is provided free of charge via email. However, no support or design guidance is guaranteed. Its use is at your own risk. So, simply fill in the form and expect a brief email conversation. (

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)

Cheers, Thomas

--
http://www.infotech.tu-chemnitz.de/~knoll/

"Antti Lukats"  wrote in message
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Reply to
Knoll

Rather heavy-handed set of restrictions, don't you think?

--
	Sander

+++ Out of cheese error +++
Reply to
Sander Vesik

Hello

There is also an english version of the description and contact form page available by now. The title is "Free VHDL implementation of a PCI Brigde using Xilinx Spartan-IIE FPGA" for the design description page and "Design reuse of the free VHDL PCI Bridge Core" for the actual contact form.

There is no direct download, but the source will be sent as attachement during a short email exchange.

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Cheers, Thomas

--

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Reply to
Knoll

That's because the licensee is paying only $100. If the licensee is willing to pay much more than that, that person can use my PCI IP core in a commercial project.

Kevin Brace

Reply to
Kevin Brace

Hi David,

That restriction is there for legal reasons. If what I am dealing with wasn't an IP core, there won't be such a restriction.

Kevin Brace

David Brown wrote:

Reply to
Kevin Brace

Now I'm curious, too. What _are_ those legal reasons, precisely?

--
GPG: D5D4E405 - 2F9B BCCC 8527 692A 04E3  331E FAF8 226A D5D4 E405
Reply to
Marius Vollmer

Hi Marius,

I believe it is theoretically much harder to enforce contractual obligation like prohibition of redistribution or the requirement of non-profit use if the licensee resides in a foreign country.

Kevin Brace

Marius Vollmer wrote:

Reply to
Kevin Brace

Given Sander's email address, I'm guessing he was objecting to one restriction in particular... and it may not have been the price. I have problems with it too... ans I'm curious - what is it there for?

- Brian

Reply to
Brian Drummond

I could live with that restriction.

I could live with that restriction.

I almost could live with that restriction as well, although would prefer direct credit card payment, as PayPal doesn't think my country worthy enough to be able to subscribe.

That requirement I find offensive. There is life outside US as well. There might even be developers that don't reside in US.

It's not the commercial project requirement that's unreasonable, as you can see from above.

PS. Sorry if I was too sarcastic, I couldn't help it.

--
Taavi Hein,
developer residing outside US.
Reply to
Taavi Hein

So, what is wrong with the OpenCores PCI?

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Especially when you concider that you also get the generic source, you have not indicated any price for that...

/RogerL

--
Roger Larsson
SkellefteƄ
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Reply to
Roger Larsson

Not the point. The heavy handed part is 'US only, no-research, pay money and return printed licence'.

You know, your licenceing is way more restrictive for which I can download the Oracle database and most of their products, and same applies to IBM and similar. Not only are your terms unreasonable, you aren't even really all that price competitive as far as one-shot PCI cores go.

--
	Sander

+++ Out of cheese error +++
Reply to
Sander Vesik

Really? You do realise that should you prototype something in the FPGA that works with that core (whetveer directly or now) you are effectively forced to *ALWAYS* start over from scratch if you want to use it in some other project? This is the sucky part about such a core - you can't get a replacement one and continue developing in that, be cause the moment you try you may be suddenly retroactively screwed from start (notice the word continue).

--
	Sander

+++ Out of cheese error +++
Reply to
Sander Vesik

The $100 license's US residency requirement is there because if a licensee violates the license agreement of personal use, and uses the PCI IP core in a commercial project in a foreign country, it is probably going to be much harder to stop that than if it happened in this country. The no-academic research restriction is there because I want to charge more than $100 for research-related academic use. If you don't like that, talk to Xilinx, because I heard that they sometimes donate their PCI IP core to universities. Regarding your "one-shot PCI cores" comment, no, mine will cost $100 more than a free one, but as a product it will be identical to a commercial version I am planning to charge much more than $100. Plus, the licensee can receive technical support through a forum in Yahoo! Groups I am planning to set up.

Kevin Brace

Sander Vesik wrote:

Reply to
Kevin Brace

I am trying to run a business (Sounds better than working at a retailer.) licensing my PCI IP core to other firms or people, so the RTL code will cost as much as a new car. As far as I know, that's how much IP core firms charge for a PCI IP core. I probably shouldn't trash Opencores.org PCI IP core here, but I believe my PCI IP core will be easier for beginners to use than Opencores.org PCI IP core because it is structually simpler, will be supplied in netlist format (As opposed to having to synthesize the PCI IP core.), and comes with a constraint file to meet setup and hold time requirements of PCI.

Kevin Brace

Roger Larsson wrote:

Reply to
Kevin Brace

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