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Synthesis problems with while and non-constant terminal point.

Hello all, I have an algorithm i would like to implement in an fpga. I have no idea of knowing how many times the 'while' loop should run.

But doing something like this seems to be illegal in verilog. Any ideas of how i can get around this? How could i implement a c-style loop in verilog?

I tried to make a simple example of this. I'me using Quartus2 Web edition for the synthesis.

integer V; integer X; always @(V) begin V = 1;

while( V ) begin V = V + 1; X = X + V;

if( X < 30 ) begin V = 0; end end end

Thanks!

Reply to
Andre Bonin
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You need to get used to thinking in terms of hardware, instead of how many times something will loop.

Think about how you would build it using TTL gates and flip-flops, for example. Once you do that, consider what your loop is doing. Making things run fast in hardware means doing many things in parallel. C style loops don't naturally do that.

Hope this helps,

-- glen

Reply to
glen herrmannsfeldt

Consider adding a clock input and use a synchronous process loop that executes once per clock.

Now, within this process, you can do as many sequential statements as you like up to the limit of the clock cycle time. A static timing analysis can check this for you after synthesis.

Step one is to get your code running synchronously and correctly in a simulation testbench.

Step two is a trial synthesis and static timing check.

If static timing fails the FMAX constraint, modify your code to do less per clock, or reduce the clock frequency.

Good luck.

-- Mike Treseler

Reply to
Mike Treseler

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