Synthesis errors?

The Quartus II 3.0 Tool from Altera has a good VHDL/Verilog parser and synthesis capability. The output of the synthesiser will work only with the place and route tools from Altera, and you target all of the Altera devices. A free version of the tools is available from:

- Subroto Datta Altera Corp.

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Every synthesizer will suffer 'cause all of them are SW and SW (as well as HW ;-) has bugs... The only solution to that problem would be to use an equivalence checker to check the generated Netlist against the RTL. They are also not bug free, but if the do not share code, the probability of having the same bug is near to 0. Tools in that area are for example Verplex LEC but there are a lot more. HTH

-Eyck

I have used a lot of the synthesisers out there and I have had errors with all of them at one time or another. I have usually tackled them in the way you describe. Usually I have found particular constructs to be the issue and generally avoid the ones that cause problems. Generally the best way to find the bugs is in a post synthesis simulation. Do this ideally with a self checking testbench that you can run on a spare machine in the background. It can be a long process on a big design.

To reduce the long synthesis/simulation times consider using modular synthesis and simulation. Some tools will do this automatically for you. Using this approach you can virtually ignore "good" modules and look for problems in the modules you have actually changed either by design or synthesis. I hope to have a article on the cheap and cheerful approach to this in our TechiTips page either this month or next.

John Adair Enterpoint Ltd.

This message is the personal opinion of the sender and not that necessarily that of Enterpoint Ltd.. Readers should make their own evaluation of the facts. No responsibility for error or inaccuracy is accepted.

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