simulating

Hello, I am relatively new to Xilinx and VHDL programming for that matter. I have currently concluded certain sections of my final design, however I need to test it by imposing signals at inputs to this design. Currently I have had to design vhdl parts that would generate these signals however I would like to these to not be synthesised with the rest of the design. Is there any method by which I can impose more complex signals on the testbench or modelsim? Thanks C