Register names in Quartus Signal Tap Node finder


using the Quartus SignalTap Node finder i encountered the following problem. When i use a graphical designfile (*.bdf) and i name the instance of a register, i.e. reg_A, then i can search for this name in the SignalTab nodefinder. When i do the same with a VHDL file and i name the register, i.e. REG_A : process(clk), then the nodefinder doesn't find the name. Instead i see something like i~0 since the name was not preserved during synthesis. So i tried to preserve the name by using the "keep" attribute for the registered signal as it is described in an older thread. But this generates an additional logic cell and changes my design.

Is there any way to keep the name of an instance/register in a vhdl file without generating additional logic cells?

Cheers, Torsten

Reply to
Torsten Alt
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Hi Torsten,

There is an explanation of how Quartus names registers in the Quartus II handbook chapter on Quartus Integrated Synthesis:

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Quartus does not use the process block name in naming registers, since many registers may be inferred in a single process block. So the register you're creating won't be named REG_A.

The 'keep' attribute is not needed to preserve register names. That attribute is used to make sure a combinational node you want to observe exists (isn't optimized away or folded into other logic) in the implemented design. The 'preserve' attribute is used to make sure registers that are duplicates, stuck at logic 1 or 0, or otherwise are unnecessary are kept in the design. However, you shouldn't need to use that attribute either, since presumably this register is not redundant.

If you post a more complete code fragment, we can probably give you some more guidance as to what your register will be named. i~0 is probably a combinational node name, since those are more difficult to keep good names for than registes.

Regards, Vaughn Altera [v b e t z (at)]

Reply to
Vaughn Betz

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