using the Quartus SignalTap Node finder i encountered the following problem. When i use a graphical designfile (*.bdf) and i name the instance of a register, i.e. reg_A, then i can search for this name in the SignalTab nodefinder. When i do the same with a VHDL file and i name the register, i.e. REG_A : process(clk), then the nodefinder doesn't find the name. Instead i see something like i~0 since the name was not preserved during synthesis. So i tried to preserve the name by using the "keep" attribute for the registered signal as it is described in an older thread. But this generates an additional logic cell and changes my design.
Is there any way to keep the name of an instance/register in a vhdl file without generating additional logic cells?