I am trying to play around with Synplify and an EDK project I have already implemented solely in the EDK. I have flagged the "IMP_NETLIST = FALSE" in all the user IP in the project. Then I use the "Export to ProjNav" in the Tools menu.
Opening the resulting "system.ise" project in the ISE tool works correctly. All the core vhdl and verilog "wrapper" files are added as sources correctly, but since the EDK did not synthesize the user IP, they all show up as "?" sources in the project.
So just messing around, I pulled in the top level vhdl for one of my IP. This is the vhdl file that the import peripheral wizard made, and the one that I filled in correctly. Again, this project works fine in the EDK, so all files for all IP's are correct.
Once I add that top vhdl file as a source, and the associated files for my IP, everything looks OK except for the opb_ipif source referenced in the vhdl file. It shows up as a "?" source. OK, so I add the source from the common libraries. So the opb_ipif looks OK, but it references sources that reference sources that reference sources, etc, etc, etc. I started adding all the sources it asked for. But then it gets down to some that are not even on the hard drive of my machine. They are nowhere to be found. So of course, the Synplicity errors out.
Is there a way to do what I am trying to do? Basically, I want the EDK to synthesize the Xilinx IP and Synplicity to synthesize the user IP via the ISE. Then I guess I would pull the finalized bitstream back into the EDK for final compilation and download.
I know I could probably black-box the user IP in the ISE first and then pull that into the EDK. But I am just messing around, evaluating what can and cannot be done using Synpilcity. It is a VERY expensive tool that we are trying to see is worth justifying.