Hello,
I have a pll clock multiplier block that multiplies and divides an input clock and uses that clock signal for my FPGA system clock. How can I bring that output to an external pin for debug monitoring as well as use it internally? I tried connecting an output port to the clock multiplier output (also connected to other internal blocks) and I get the following error, when attempting to synthesis the design:
Error: ClockLock PLL altclklock0:inst10|altclklock:altclklock_component|outclock0 must feed only one CLKLK_OUT pin
Any ideas why and how to fix it?
Thanks Salman