PLL lock usage into Altera Stratix devices

The PLL will lock AFTER configuration, so after configuration (or a circuit break or so), lock will be deasserted. Also note that the lock signal is direcly derived from the phase comparator, so while the PLL is locking, you'll see the lock pin be asserted and deasserted a few times before it becomes a stable '1'.

The best solution is to have a counter that counts up to some value as long as lock is '1', and gets reset when it becomes '0'. Once it reaches the count value (say 31) it should stop counting and tell the logic that the clock is stable, which I think is easiest to achieve by ANDing this signal with the (synchronous) reset signal for the circuit.

Best regards,

Ben

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Does that mean we have to do this in every design that uses a PLL? Can the FPGA be driven (and therefore violation setup times) with a too fast clock during PLL startup ? I didn't care about the PLL lock till now, just inserted it in the clock path.

Martin

---------------------------------------------- JOP - a Java Processor core for FPGAs:

I thought this is already common sense. And with an FPGA you need no external reset at all. To be on the safe side (as you suggested) take a small counter till you release the reset signal.

Martin