DSP question , cascading functions

RealInfo schrieb:

filtered and the 2nd DSP function will be done on the

Hello,

that is a problem of the sampling frequency and the time needed to compute the first and the second function. If the sampling requency is

Bye

function

be filtered and the 2nd DSP function will be done on the

can it not be 'pipelined' and simply delayed? The first function is a simple low pass, of sorts. Memory would only take enough memory samples to represent the low frequency cutoff, right?

function

filtered and the 2nd DSP function will be done on the

If it's a uP, you don't gain any compute power from pipelining. If it's done in an FPGA, you can pipeline many, many clocks. One can also clock the early stages of a lowpass filter at a higher rate than later ones.

Come to think of it, one can do that in software, too: run the first stage or so more often than later ones.

At any rate (pun!) there's no need for filtering between DSP functions; just stack them up.

firs function

should be filtered and the 2nd DSP function will be done on the

is

within

done in

early stages

stage or so

just

Just the same, the only real question is can you get all the tasks done on time. This is a simple hard real time thing. OTOH the comm time to hand it off to a second DSP for the next stage may kill the timing.

?-)