The question is "Has anyone successfully integrated two DDR SDRAM controllers controlling one block of ram?"
The alternate approach is to use the DSP HPI port as the transfer port between the shared SDRAM and the DSP. This would not rely on using the DSP DDR SDRAM controller to access the shared ram. The bandwidth takes a hit but the overall system preformance is not affected. Oh the internal memory of the DSP is large enough to hold program and data.
The System: The system consist of a Cyclone or Stratix FPGA with a NIOS II, DMA and a DDR SDRAM controller internal to the FPGA. External are a TI DSP capable of being a DDR SDRAM controller. There is a block of DDR SDRAM shared between the FPGA and the DSP. The shared ram is for data exchange between the NIOS and DSP. After spending a few days looking over the ram, DSP and DDR SDRAM controller documents I'm thinking that the simplest approach to integration is to use the DSP's HPI port for data transfers between the shared memory and DSP. The HPI can be ran under DAM and has buffers both for read and write . While this approach isn't the fastest I think it has the best chance of working. The timing for the ram is tight, the control signals are slaved to the differential clock (implies switching the source of the clock between the FPGA and the DSP), debug nightmare and something I wouldn't want to argue in front of a peer review board.