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Re: Storing a file onto FPGA (the last word)
Hi John,
...and I spent so much time with that nasty data2mem tool... :-(

But it's good to hear that an alternative and more straightforward
solution exists, even if it's limited to XILINX.

The bad thing is that it can't be taught in VHDL courses unless it is
supported by many (at least the important) tool vendors. Until then we
have to deal with questions like that of Robert.

I hope this feature finds it's way into VHDL 20xx and will be supported
by more tool vendors much earlier.

Thank you John for the information. (And to the XILINX programmers as
well. It's the first positive feature of the 7.1 version up to now IMHO.)


John McCluskey schrieb:
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-- snip
-- sorry, needed to cut to old post

Re: Storing a file onto FPGA (the last word)
well if it can't be taught in schools.. shouldn't the schools get a student
to write a better one ??


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Re: Storing a file onto FPGA (the last word)

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Cool!  I didn't know that they had actually implemented it.  Now if
Synplify would follow suit, it would
surely get filtered into the other fpgA tools over time.  The write
seemed like a logical extension, although
I'm not sure how useful it is beyond writing a serial number or key to a
file at compile time.  Hmm, it
may be a (albiet, kludgey) way to pass a propagation delay or latency
back up to a higher level in the design hiearchy.

--Ray Andraka, P.E.
President, the Andraka Consulting Group, Inc.
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Re: Storing a file onto FPGA (the last word)

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Alas, I've thought of this already, and it will only work for iterated
synthesis.  If you think about it for a second, you'll realize that the
language semantics force elaboration from the top of the hierarchy down to
the bottom.  Generics have to be fully calculated before the subcomponents
can be elaborated.  If you have a generic parameter which depends on a
value created during elaboration of the subcomponent, then a dependency
loop will be created.   This is not necessarily a bad thing, but the
programmer will have to be aware of it, and make sure to stop the
iteration of the elaboration of the subcomponent (at some point).  I'd
really like to work out a design flow where this is possible, but right
now, this will require scripting a control structure to iteratively call
the synthesis tool to compile the subcomponents with specified generic
parameters.   I think that right now, XST doesn't accept top level
generics as command line arguments :-(

Bottom line:  It's really tough to write code that explicitly supports
multiple topologies that can automatically be explored at compile time to
close timing.  VHDL needs to be extended to support design space
exploration, as well as to support physical timing feedback into the
elaboration control structures.   It'll probably take the rest of the
decade to get something going with Accelera along these lines.  

John McCluskey

Re: Storing a file onto FPGA

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Others have pointed out most of the pieces.

1) With XILINX, for the actual FPGA use a BMM file and data2mem to
initialize the rom contents in the bitstream.  It's a pain to figure
out and I last did it a year ago so I don't remember the details, but
when you get it all worked out put it in a makefile that runs your
table generator, updates the bit file and downloads to the FPGA.

2) For simulation, write a program that generates verilog code to
initalize the memory.  Yes, XILINX makes you initalize it a different
way for simulation than for synthesis.  Unlike apparently VHDL, verilog
has an include directive, so you don't have to have your code generator
recreate an actual verilog file each time, it can just spit out the
file with the initialization commands.  Put this in a makefile too...

This is pretty much the same problem as how to load ROM contents for a
custom embedded processor (ie, one where you aren't using embedded
development tools that handle the whole deal for you)

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