Advice to a newbie

I a retired person with limited resources and I've always been
interested in CPU design, so now that I have time I wanted to give it a
go using FPGAs to design simple CPUs.
I would like some advice on several topics, one being which HDL language
to learn first, although Verilog seems simpler I've read articles that
encourages beginners to start with VHDL, although it seems more wordy, I
believe it will help eliminate more dumb mistakes so I'm leaning that
way. What is your advice?
Another is which logic families/companies make products that are
inexpensive and have good features useful in creating CPUs and DSP type
products as I also am interested in Software Defined Radios.
I have purchase for a starter kit a Lattice Brevia2 kit as it was
inexpensive and has low power consumption, so I assume will be easier to
use in the beginning. It's a simple device with 5K LUTs which seems to
be enough for some of the simple processors that I'm interested in to
start with, CPUs such as the J1 for starters. From some time back I've
have a Xilinx Spartan 3 Started kit that I have not used, I plan to use
it later for more complex designs.
Your opinions and advice is welcomed.
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Cecil - k5nwa
Reply to
Cecil Bayona
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Verilog if you're on the west coast, VHDL if east. I'm not sure about Texas, though.
Seriously, it's a lot more important to understand how to design than to pick the right language. You can do crappy work in either one, and you can do good work in either one.
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Tim Wescott 
Control systems, embedded software and circuit design 
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Tim Wescott
Hardware design I understand, I put together my own CPU design and built it with Schottky logic, and it worked rather well. But as to Verilog or VHDL I know zip. I do have a couple of books on the subject of FPGA programing but I don't think of them as any good. They go into the tiny details such on how to make an adder but contains little on the overall structure and how to design anything of consequence.
Are there any books or Internet sources on the subject of overall design with FPGAs? I would be specifically interested on CPU design using HDL.
Thanks
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Cecil - k5nwa
Reply to
Cecil Bayona
Look for books with "Computer Systems Architecture" either in or as the title. they will not and should not mention FPGAs -- by the time you're making architectural decisions you probably shouldn't be too worried about what the underlying technology is.
Then, get your hands on data sheets for as many different processors as you can and see how they did it. Think of strengths and weaknesses, and why the designers might have done what they did.
And let me indulge myself with a shout-out to the RCA COSMAC 1802 processor. It was the first thing I ever wrote assembly for, and you could practically draw the control logic from the instruction set. I dimly remember (meaning that I saw it between two days and two decades ago) that there's an FPGA version of the core that's at least byte- accurate, if maybe not clock-cycle accurate. In these days of RISC computers, it's nice to be familiar with a NHISC (Never Had an Instruction Set) computer.
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Tim Wescott 
Wescott Design Services 
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Tim Wescott
Cecil, here's a very simple 8-bit CPU I designed, called Oppie-1. It compiles in Verilog and in Altera's Quartus II software. I have not validated it, so it's probably buggy. But, it may be interesting to look at it.
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Best regards, Rick C. Hodgin
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Rick C. Hodgin
It looks like I didn't make myself clear enough on what I was looking for, I was looking for books or articles on FPGA programming that discusses how to use the software to program the FPGA to create CPU features. I already own a few books and have many articles on CPU architecture, plus books and literature on CPU instruction sets.
Is there literature,basically a primer on how to create a simple CPU in HDL, preferably in VHDL?
The alternative is that I will need to do it on my own by looking at a simple example such as the J1 , ep16, or the B16 CPUs and see what they are doing to create the CPU hardware blocks. The J1 is a pretty simple CPU done in less than 250 Verilog statements, the instructions are are bits controlling the various hardware features with no decoding of the instructions.The J16 is done in VHDL using a Lattice Brevia2 so it should run as is, the disadvantage is that it's more complex plus it's created by someone who is not very experienced. All three already have a compiler available to write software to test them.
The disadvantage to all these simple CPUs is that there is no documentation to the software that creates the devices so as a rank beginner it will be difficult to see what they are doing.
Thanks
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Cecil - k5nwa
Reply to
Cecil Bayona
Sorry it the ep16 instead of the J16 that is in VHDL and uses a Lattice Brevia2 board.
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Cecil - k5nwa
Reply to
Cecil Bayona
This does not directly address your stated issues, but there is a workshop Saturday. Notable is that it will use the same starter kit you have. I believe you can participate via the Internet. It might be interesting to you since it is about CPU design. Here is a post I made about this in another group.
Dr. Ting will be leading a workshop on using a Lattice FPGA to implement an emulation of the 8080 instruction set which will run Forth.
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I believe you need to be a member of Meetup to see this page. I'm not sure but you may need to be a member of the SVFIG meetup group as well. There is no charge to join either.
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Rick C
Reply to
rickman
]>The disadvantage to all these simple CPUs is that there is no ]> documentation to the software that creates the devices so as a rank ]> beginner it will be difficult to see what they are doing.
Did a presentation in March directed towards this problem. The idea is to do the simplest possible soft core processor (done here in VHDL). It helps to use the fewest lines of code. The PDF of the slides is at:
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"DIY soft-core processor" Full VHDL code is available on the Overview section. Only four instructions are implemented (didn't want to make it too easy for students).
If you enjoy doing test cases and would like to help, send an e-mail.
Jim Brakefield
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jim.brakefield
Thanks, I already joined, that is the reason for buying the Lattice Brevia2, I will be watching the meeting, but the video is supposed to be available afterwards so I can take my time afterwards and go through the course at my pace.
I loaded Diamond on a Virtual Windows 7 partition and setup the ep8080 project and noticed that the software warned of a clock issue, Dr Ting mentioned that he was having issues where if he made changes things would break so that clock issue might be related.
I been looking at some video courses and they had a lot of information on translating a set of hardware into VHDL code, so over the next few weeks I will be trying the lessons to become familiar with VHDL. In the meantime I will also be looking for books on VHDL and how to use it to create hardware.
I have done hardware design some time back and I still like doing so but I'm hoping that once I become more familiar with FPGAs I can do more experimenting as buy once and try out many times is perfect for experimenting.
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Cecil - k5nwa
Reply to
Cecil Bayona
Thanks for the link, I will look at it this weekend, every little bit helps.
I watched a series of YouTube videos and there is hope, a small project but not idiot simple and done by hand, it didn't seen as alien as I thought it would be. The person basically designed the hardware and then proceeded to generate the program with explanation of what he was doing, of course the devil hides in the details but still it looked logical and not difficult. So after the weekend I will try it out. This weekend I will be following a seminar on the ep8080 CPU, a high performance clone of the 8080 CPU not only does it run at higher speed but most instructions execute in one clock cycle, it should be interesting.
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Cecil - k5nwa
Reply to
Cecil Bayona
I have not seen any books on this topic, but then I haven't looked. My approach is not study the architectures of various approaches to soft CPUs and adapt to suit my needs. I did some work on a MISC (minimal instruction set computer) around 2001, 2002. I found that there were others doing the same thing and we were all discovering the same issues. Our approaches differed mainly in what our priorities were.
I ended up dropping further work to a large extent. I did play with some ideas a few years ago regarding an architecture that included fields in the instruction for small offsets from the stack pointer to try to combine the advantages of register and stack machines. I think it has potential for working well at the hardware level. I just don't know enough about compiler writing to program this device from a compiler. Maybe I'll get back to this again some day.
In the meantime, I suggest you work with existing CPU designs to learn what they have done. No point in reinventing the wheel. The group comp.lang.forth has a few folks who have designed their own CPUs which you seem to already be aware of. However, this is a good group to discuss your issues.
I would not worry about the target device. The HDL isolates you nicely from the hardware unless you wish to highly optimize the design for a particular FPGA family. The fact that some design was implemented on a Brevia2 board really doesn't matter and can also be run on a Spartan, Cyclone or Fusion.
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Rick C
Reply to
rickman
Ages ago I had a notion about combining the advantages of register and stack machines, which was to call the region of 16 addresses around the stack "registers", and to have the processor automagically cache them on a context switch. The idea was that the code itself wouldn't have to specify registers to save on push and pop because the processor would do it automatically.
I'm pretty sure I had not yet seen, nor independently conceive, the RISC- ish push & pop of multiple registers in one instruction.
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Tim Wescott 
Control systems, embedded software and circuit design 
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Tim Wescott
I've found a couple of YouTube videos to help me get started, I'm looking at Amazon for books on the basics of VHDL so I'm sure that I will find enough to get started, the videos made it look easy if you are familiar with hardware design.
That is my plan, I mentioned several simple CPUs before that are very small, and have software available to be able to test them without re-inventing the wheel. I would get them going, try to understand then, then start making modifications, then create one from scratch, simple at first then add improvements, it will take a while but that is part of the learning process.
For most of what I'm interested in you are right, mostly simple architectures that are lean and mean with nothing fancy, memory, registers, ALU units, and multiplexers, everybody has those devices, some boards have lot's of IO devices such as VGA, external RAM, etc but for now all I need is some RAM, and a serial port which the Brevia2 already has.
An exiting adventure, I should have started on this earlier but today is better than tomorrow.
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Cecil - k5nwa
Reply to
Cecil Bayona
I think the need for a book is a bit overrated these days. I haven't opened a VHDL book in ages. When I don't recall something or I want to learn about new features (VHDL 2008 has many) I just do a google search.
You can also get plenty of help here and in c.l.vhdl.
What is your end goal? The main reason I quit working on my own was that I was not finding much room for improvement other than application specific features or optimizations. The target space has been explored pretty well at this point.
The J1 is a great little processor. Then there is the ZPU which doesn't come up much in Forth circles, but is a stack machine programmed in C.
The workshop should have started by now. I haven't see an email from SVFIG yet.
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Rick C
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rickman
Found it. I had to search youtube for "svfig may"
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Rick C
Reply to
rickman
I bought a couple of used VHDL books on Amazon for good prices. I agree once you get going the need for the book diminishes that is why I bought used books, the Internet is a good source of information once you know the basics.
My end goal is simple, I do it for my pleasure, no vital need here other than keeping your mind active and busy. I enjoy creating things so this will go a long way to satisfy that desire without a whole lot of expenses.
I will look into the ZPU, I saw some references to it but I will look into it, I have two choices to start with, the J1, and the ep16
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Cecil - k5nwa
Reply to
Cecil Bayona
Thank you for posting this information, Rick C. I've watched some of the content that's available on YouTube from the event. It's very interesting.
Best regards, Rick C. Hodgin
Reply to
Rick C. Hodgin
Thanks for the info, but I was aware of the workshop and bought the Brevia2 so I could participate in the workshop, I missed part of the afternoon session as an emergency cropped up but I was planning on later in the week watch the video and follow along. with the video I can stop, wind back and take my time in following along. Previous to the workshop I loaded the software and got it working, so my goal is to go over the explanations on what the different sections do.
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Cecil - k5nwa
Reply to
Cecil Bayona
I have several book on the way that are used and cost little so between them I should have plenty of information. I also got two used books on computer architecture that look interesting for next to nothing, overall I paid $54 for 7 hard bound books, some are new, or close to new in condition. I also went through my bookshelf and I found two books that look decent, one looks pretty nice it goes through the feature of VHDL on their use, "VHDL Made Easy". The second one is "HDL Chip Design" and it looks very useful, it goes discussing various hardware features and covers how to implement them in VHDL, and Verilog. Both books are brand new that I purchase on Amazon for less than $10
So it looks like I will have a decent reference library for not much. This coming week will be time to experiment. I've setup a Virtual Windows 7machine with VMware on two I7 PC's and they seem to be working fine.
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Cecil - k5nwa
Reply to
Cecil Bayona

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