VHDL Verification components ? The obvious solutio n to efficient reuse

How would you assure safe and efficient reuse of an FPGA design module for
some stand-alone functionality?
Let's consider this for a simple example like a UART. Now what would you do
You could of course just make lots of functions, procedures, processes and
concurrent statements, - and then include all of this into your FPGA top-le
vel whenever you need a UART... But no serious FPGA designer would ever d
o this.
Why? Because we all know it is much better to put all of this into a comp
onent (a VHDL entity), as this has the following benefits:
- Everything is encapsulated in an entity containing all needed elements
- No risk of forgetting parts or functionality
- No need to understand the implementation
- A simple port interface for integration into the FPGA top level
- A simple generic interface for parameterisation of the module
- Internal modifications may be done locally - invisible at the FPGA top le
- New functionality may be added inside the encapsulation
- Reuse is safe and efficient
Now - give me one reason why all of this does not apply to verification exa
ctly the same way.
Yes - we could still just use lots of processes, sub-programs, etc, but as
for design that would be very inefficient and risky.
What we need is of course a VHDL entity - a VHDL Verification Component (VV
C) - encapsulating the complete verification functionality for a given desi
gn interface, where the VVC should be characterized by:
- An easy to understand component interface (ports and generics)
- A clearly defined internal functionality, where the internal implementati
on is of no interest when integrating the VVC
- An easy to understand command interface to control and monitor the behavi
our of the VVC
This is exactly how the VVCs of UVVM (Universal VHDL Verification Methodolo
gy, free and Open source) are made.
(For a figure of the UART VVC please see
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The VVC for a UART has two simple physical port (TX, RX), and is thus very
easy to integrate in a testbench. All the functionality is included inside
and thus well encapsulated and easy to reuse. Once included in the testbenc
h the test sequencer/driver/controller may then execute commands to transmi
t and receive data in many different ways. This command interface is predef
ined in UVVM, which thus provides a common and standardised way of communic
ating with any VVC independent of type - again just like a CPU may communic
ate with any design module inside an FPGA via a predefined bus interface.
A major additional benefit of the UVVM VVCs is the ease of integration, the
very structured internal architecture and the extreme reuse friendliness.
UVVM is free and open source, and may be downloaded from Github: https://gi
For a simple and fast introduction to UVVM and VHDL Verification Components
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Espen Tallaksen
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