Sharing VHDL Verification IP

Sharing VHDL Verification Components (VVC) within the FPGA/VHDL community h
as previously been difficult because there was no standardised way of inter
facing to and controlling these VVCs. A solution on this challenge could ea
sily reduce the project verification time by 20 to 80%, and at the same tim
e improve the FPGA quality.
The open source UVVM has over the last two years standardised the command i
nterface, integration, debugging and internal architecture of VHDL Verifica
tion Components and clearly shown that a standardisation was in deed both p
ossible and extremely efficient. Open source VVCs have been released for AX
I4-lite, AXI4-stream, Avalon MM, I2C, SPI, SBI, UART and GPIO, - showing ho
w easy it is to implement testbenches and write test cases using this stand
ardised methodology.
Due to this standardisation, FPGA designers world-wide have recently starte
d asking for more cooperation on UVVM compliant VVCs inside the VHDL commun
ity. As this is actually the main intention behind standardising VVCs, we h
ave now decided to facilitate a Verification IP cooperation. For this purpo
se we have opened a new repository on Github for sharing VHDL VIP next to t
he UVVM repository.
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This new repository is intended to link to any UVVM compatible Verification
IP; - VVC, BFM or other. We have chosen not to include any VIP directly in
side this repository, as all 3rd party VIP will be the property of and main
tained by the 3rd party company or designer.
Any 3rd part VIP will automatically be UVVM compliant given that the design
ers have used the provided templates or scripts from UVVM. This has of cour
se the major benefit that all UVVM compliant VIP can be controlled and acce
ssed exactly the same way and that they will work together. There is howeve
r no way we can guarantee the functionality of the DUT interface/protocol h
andled by 3rd party VVC or BFM designers, so this will be the full responsi
bility of the VIP provider. Any question regarding the VVC should therefore
be addressed to this provider. Bitvis will not qualify any 3rd party VIP,
but we assume the community will very soon give useful feedback.
Open source Verification IP is great, and UVVM with its provided BFMs and V
VCs are all open source and free, - but we also welcome commercial VIP and
will link to this in the same way as open source. It is important for VHDL
designers to get the full overview of what is available, and it is up to th
em to decide whether a commercial VIP is ok. All commercial aspects must be
handled directly between the buyer and the seller. Bitvis has no role in t
his.
Note that even if UVVM has standardised the VHDL testbench architecture for
efficient verification, you may still pick only the parts you like. Thus y
ou can pick only a single BFM or VVC from UVVM if you like, and use this in
your testbench together with your own and 3rd party verification IP.
We now really hope that the VHDL community will use this opportunity to mak
e us all more efficient. Have a look at this on Github and start the proces
s :-)
(This article was also published on LinkedIn. Articles there may also inclu
de figures, which sometimes is very useful...
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Reply to
Espen Tallaksen
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