signals inside a process

Hi,

It depends on exactly what you are trying to do.

If you want to save the input SAMPLE_IN signal(s) on every rising edge of clk and then only transfer the results to the output (max_sample_result for eg.) when symbol_clk_edge is high, then you need to break the code into 2 processes as follows.

process(clk) begin if (clk'event and clk='1') then -- Sample inputs and store in temp registers max_sample_temp if (symbol_clk_edge='1') then

value

Yes they all execute at the same time, i.e. the rising edge of clk. But... if you look at it like a simulator, the order of operation is:

1. sample all inputs (right side of equation)
2. generate output values from the logic (here these are all simple assignments so output values come from sampled inputs directly)
3. update all outputs from the generated values. So... all outputs change at the same time, but using the input values from before any change occurs. This is how flip-flops work in real life.

Try the code just as you wrote it.

I would like to assign TEMP value to RESULT at symbol_clk_edge and reset TEMP to SAMPLE_IN value. The most important for me is to store last value of TEMP to RESULT before resetting it.

I'll try using it again as I did write originally. I had some problems with this implementation though. That's why I've posted the question. Sometimes at symbol_clk_edge, RESULT would be assigned with SAMPLE_IN (bad), and sometimes with TEMP as I want it. But also, it looked like there was no delay between SAMPLE_IN and RESULT or TEMP!! maybe because of that? SAMPLE_IN is a port TEMP, RESULT are signals. ?? I'll try assigning port to signal first. Maybe it will create a proper 1 CLK delay.

Hope that helps

That sounds like you are thinking with your software hat on.

In hardware, you want to do both on the same clock. I'd expect you would have a clock-enable for loading RESULT and you could use the same signal to on a mux in front of TEMP to force loading SAMPLE_IN_value rather than maybe keeping the old value.