using I/O pins as chip enable

An I/O pin cannot be used as a memory chip enable if the memory's address and data lines are connected to the processor's address and data busses. Doing so would certainly violate the processor's bus timing requirements.

Consider, for example, a reading the memory. The processor fetches the instruction that sets the chip enable from memory, then releases the busses, and executes the instruction. The memory, now enabled, drives the data bus with the data at whatever location happens to be on the data bus at the time. The processor now wants to fetch the next instruction and this will contend with the memory.

If the memory's address and data lines are driven by other hardware, though, it may very well be appropriate to drive its chip enable with an I/O pin. But I'm not coming up with an circumstances in which this might be useful!

There are memory and peripheral ICs that still have more than one chip select inputs. On those, it is possible to use an IO pin as a bank (or IC) selector. But that's the only instance I can quickly recall that would be different than what you said. Unless of course, you add additional logic to the existing chip selects.

Noel

not strictly true.

usually chip enable is connected to the address decoder, if you only want to have one chip at a time active on the bus you can use an I/O for that purpose.

Bye. Jasen