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FPGAFLASH

Some years ago, a XILINX project was "Designed by Jens Hildebrandt, University of Rostock/Germany, 2002", as it says. The purpose of this piece of work was to enable one, by means of a CPLD, to program a FLASH memory via an ASYNC serial link, and, after changing the state of RTS, to use that FLASH memory to provide the bitstream and controls to program a XILINX FPGA.

Unfortunately, the portion of this that I received did not specify anything about the external interface.

Has anyone had experience with this project, to the extent that it's been implemented? If so, can you advise me as to how this scheme can be implemented in hardware?

thanks in advance

Reply to
edick
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Haven't seen this particular APP, but I've used Xilinx's XAPP 800 (with a

95XX series instead of a CoolRunner, up & running in no time). Worth a look, though it isn't programmed serially but rather with the Parallel IV cable.

Cheers, Alf

Reply to
Unbeliever

AFAIK, the device in the FPGAFLASH APP was a 9572 or thereabouts. It was not specific. I've some doubts about that, since it didn't seem to have enough data to ensure there were sufficient pins available with which to parallel-program the FLASH in question. The use of SPI flash raises some question as to wherether (a) there are any SPI devices large enough to be of use for programming medium-sized FPGA's, e.g. Spartan3's in the range up to 1Mgates, and (2) whether there's a really convenient way to program the SPI flash.

I've not yet studied out the details, but I do like the fact that this approach doesn't require the serial port levels. Goodness knows that current generation FPGA's already require enough power supplies.

thanks for your comment.

Dick

Reply to
edick

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