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adding SDRAM to the S3 starter kit

Hi all,

I'd like to create a plugin for the S3 starter kit board that adds (say)

32 or 64 MBytes of SDRAM via ports A1 and A2. Not having much experience using (for me, at least) such high frequency parts I was wondering if it was even possible...

I'd like to run the microblaze processor synchronously, so clock frequency will be ~87MHz. I was thinking of using plain jane SDRAM not DDR SDRAM because it's simpler (although perhaps if I use half the cpu clock speed, it might make it easier on the signal integrity ?) I'm assuming that (as long as I meet the SDRAM refresh requirements) I can scale down the frequency to suit the processor.

I downloaded XAPP134 (the only one I could find that dealt with SDRAM :) and I'm having some problems understanding table 8, Hopefully Xilinx won't mind me reproducing it here. The timing terms aren't defined - I guess I'm supposed to know already. Oh well :-(

Device T(OH) T(AC) T(SU) T(HOLD) T(CYC) SDRAM-8 3.0 6.0 2.0 1.0 8 ns (125 MHz) Virtex 1.0 3.9 1.7 0.0 8 ns (125 MHz) S31000 2.95 0.0 11.5ns (@ 87MHz)

To try and understand the timings, I was comparing the datasheets for Virtex and S3, and I *think* the T(SU) of the virtex (labelled as T(PSDLL) in the Virtex datasheets) is the same as T(PSDCM) for the S3, SU presumably refers to SetUp. I couldn't find equivalent correlations for OH or AC though. CYC is pretty obviously the clock frequency :-)

In any event, the worst case timings appear to be on a read cycle, where

SDRAM T(AC) + board delay + S3 T(SU) < T(CYC) 6.0 + board delay + 2.95 < 11.5 board delay < 2.55 ns

This gives hope, even with the board's physical layout resulting in the SDRAM signal lengths being around 4 or 5 inches from the S3. Getting source termination resistors even vaguely close to the FPGA will be impossible though - I'm not sure how important this will be.

Any help much appreciated - am I even in the right ballpark ? I feel as though I'm building a house of cards in an earthquake zone [grin] The XAPP refers to IBIS models and board design tools to help, but I don't know how to use the models or what benefits they'd give me - if they'd be useful, I'd appreciate a pointer to a decent tutorial or 'howto'-like document...

Thanks a bunch for any input :-)

Simon.

Reply to
Simon
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While it _may_ or may not be possible, I'd recommend against it. The A1 and A2 connectors are not well suited to high-frequency signals. There are few ground connections.

The best use of time and money is probably to use one of the other Spartan-3 development boards on the market that already include SDRAM or DDR RAM already designed into the board. Here are a few examples. I'm sure that there are others out there.

NuHorizons HW-AFX-SP3-400-DB ($199)

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XC3S400, 64Mbits SDRAM

XESS XSA-3S1000 ($199)

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XC3S1000, 32Mbyte SDRAM

Memec Design Spartan-3MB ($795)

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XC3S1500, 16Mx16 DDR SDRAM

--------------------------------- Steven K. Knapp Applications Manager, Xilinx Inc. General Products Division Spartan-3/-3E FPGAs

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--------------------------------- The Spartan(tm)-3 Generation: The World's Lowest-Cost FPGAs.

Reply to
Steven K. Knapp

Mmm. I meant to ask about that actually - I've seen it raised before. I was intending to use the starter kit board to develop/debug individual peripherals before taking the plunge and building my own. It seemed to be easier to debug any problems on a known-working board - just to remove one of the variables.

I've been looking - the problem is that all of them seem to use a 16-bit interface to memory, and while I could write an interface that fetched 2 words before returning it to the microblaze (use burst mode, hold of RDY until both returned, done), it wouldn't model what I ultimately want, and of course it'd be slower :-(

The Xess one was looking perfect (the '1000 part, SDRAM, no ethernet, but it had enough pin headers to add it). It even had a 3 bit/colour VGA resistor DAC rather than the S3 1 bit/colour interface. But the memory is only 16-bit. Why, Dave, WHHHYYYyyyy? [grin]

The to-be-released S3E starter kit has 32MB DDR SDRAM (though whether it'll be 32-bit wide remains to be seen), but the Xilinx board is 'only' half the size, using the 500k part. I assume others (digilent) will step in and up the gate count.

There's the broaddown-2 board (except I've just moved away from the UK to the US, typical!), with tantalising hints of a lower-cost version being released soon. Even the AVnet S3 development kit board ($750) has a 16-bit interface to the SDRAM (but a 32-bit interface to its' SRAM!) These guys have no excuses, there are god-knows-how-many spare i/o on that board ...

[Sigh], if the ground issues on A1/A2 are likely to cause problems, then perhaps the slow-but-steady double-read approach might be better...

Cheers,

Simon.

Reply to
Simon

Take a board that uses 16bits DDR like the Memec one. In one clock cycle, you have 32bits. Or clock your SDRAM twice as fast (66Mhz Microblaze and 133Mhz SDRAM). Any way on a S3 you can't clock the Microblaze up to the frequency supported by your SDRAM. Even running it a 87Mhz seems in the high limit.

Also, why write the interface ? You could use one of the EDK. I know the one for DDR (opb_ddr) is part of EDK.

Sylvain

Reply to
Sylvain Munaut

It had occurred to me to clock the microblaze at 'only' 66 MHz, and clock-double the SRAM. That would probably be fine, in fact, but it seemed a bit of a waste to "lose" 20MHz of CPU frequency. The 87 MHz comes from their selection options, nothing more - I don't actually know if it really runs that fast, but they do claim 85 (I think) in their literature for the S3.

I wasn't actually aware about the supplied DDR IP - The kit only arrived on Saturday [grin]. If it's there and it works, then that's probably the way I'll go. I didn't really fancy trying to make the S3 do fast DDR access - from what I've read you need to play tricks that are under NDA in order to get it to work.

Cheers,

Simon

Reply to
google

Yes, it's the claimed max frequency. But often when I add some IP around it I can't go more than 70 Mhz due to the IP ...

Just add opb_ddr in the design, not a big problem ;) Of course creating a controller yourself that can go up to DDR400, there it's a little more difficult and the appnote describing that are under NDA.

But there is no DDR in the started kit and don't count on adding some externally. DDR has a minimum frequency and the connectors on the starter kit will kill your signals integrity. And you also need

2.5V for DDR ...

Sylvain

Reply to
Sylvain Munaut

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