Hello ,
I am an engineering student and am working on testability issues in FPGA devices. Can anybody throw light on the BIST schemes used by Xilinx in their devices ; i.e. how do they achieve 100% fault coverage;whether they use soft BIST or hard BIST. Any information will be appreciated. Thanks in advance.
Regds. Varun
Varun,
Search the USPTO for our patents on BIST in PLD.
Aust> Hello ,
go to google.com and enter: BIST Xilinx and you will find over 2000 hits. Have fun! Peter Alfke
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