Hi,
I am newbie in FPGA field. I am trying to implement look up table based logic on Xilinx FPGA. I want to implement the look up table in distributed RAM and to connect the output of RAM to implement the logic in LUT. And to get reconfigurability modify the RAM content at run time by soft core processor on the same chip. Can anybody let me know if it is feasible or not.
Thanks, Indra