timing in xilinx fpga

Have you looked at the nets in the FPGA editor to see if they are truly taking similar paths?

Also, see the following thread:

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/Andreas

Reply to
Andreas Ehliar
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Hello everybody,

I am using Xilinx Timing Analyzer in order to see average delay per each wire type, i.e. for double, hex, long and single in Virtex II chips. I found two nets where the number and the type of the wires used in the both nets are absolutely the same and they pass through the same number of switch matrixes. However, the difference in the delays of these two nets is more than 300ps. Could someone tell me where does this difference come from?

Thanx in advance!

Ruzica

Reply to
Ruzica

Hello Ruzica, The 4 (?) inputs to the LUTs each have a different delay value associated with them. They're built as a cascade of muxes. Cheers, Syms.

Reply to
Symon

thread:

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Yes, I've looked at the nets in the FPGA editor and they are indeed taking similar paths. In fact, these two nets have the same source CLB and the same destination CLB (different slices tough), but one goes first to the east and then to the north and the other vice versa, first to the north and then to the east.

Ruzica

Reply to
Ruzica

everybody,

Hello Symon,

300ps seems like a lot of time to me. Is it possible that this time difference is only due to the different inputs of the LUT?

Greetings, Ruzica

Reply to
Ruzica

Often the destination can determine a large difference in delay - the four LUT inputs are not the same!

THe HEX and DOUBLE lines are not necessarily the same delays unless you're using the same HEX or the same DOUBLE in two different CLB destination/source pairs.

The path chosen within the routing box will vary greatly depending on the specific path chosen.

Reply to
John_H

Hi, Do you have the FPGA Editor software? Open it up, try swapping the pins and see what happens to the delay. The program can report delays for you. HTH, Syms. p.s. Don't forget to report back what you find! :-)

Reply to
Symon

As I am using cores, FPGA Editor doesn't allow me to change the pins, but I will try to do it with some other design. When I get some results, I'll post it here. Thanks!

Reply to
Ruzica

Ruzica ,

Remember the FPGA Editor is a fiction.

It is a software version of the hardware.

It has no basis in reality, but is a complete abstraction of what is really there.

That said, there is serious 'magic' that happens underneath, and if you are really interested, you will have to get a job here working for us.

Austin

Reply to
Austin Lesea

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